2.1.2. MBIST controller implementation

The MBIST controller block shown in Figure 2.5 consists of:

Figure 2.5. MBIST controller block


This section describes:

MBIST controller and dispatch unit interface

The MBIST controller and the dispatch unit communicate using the following signals:

MBISTTX[11:0]

This signal is an output of the MBIST controller that goes to the dispatch unit. Table 2.7 shows the signals.

Table 2.7. MBISTTX signals

MBISTTX bitDescription
0Reset address
1Increment address
2Access sacrificial row, used during bang patterns
3Invert data/instruction data in
4Checkerboard data
5Write data
6Read data
7Yfast/nXfast
8Direction
9Enable bitmap mode
10Increment go/nogo dataword selection
11Latency stall control

When the instruction shift is enabled, data shifts between the two parts of the BIST engine are on bit 3. In run test mode, this bit is used as invert data information. The MBISTTX[11:0] interface is ARM-specific and intended for use only with the MBIST controller.

MBISTRX[2:0]

This signal is an output of the dispatch unit that goes to the MBIST controller. The behavior of MBISTRX[2:0] is ARM-specific and is intended for use only with the MBIST controller. The address expire signal is set when both the row and column address counters expire. Table 2.8 shows the signals.

Table 2.8. MBISTRX signals

MBISTRX bitDescription
0Address/instruction data out/fail data out
1Shadow pipeline empty
2Nonsticky fail flag

MBIST controller block top level I/O

The top level I/O of the MBIST controller consists of the cache controller interface. See Appendix A Signal Descriptions, and the inputs and outputs that Table 2.9 shows.

Table 2.9. MBIST controller top level I/O

SignalDirectionFunctionValue, MBIST modeValue, function mode
MBISTDATAINInputSerial data inToggle0
MBISTDSHIFTInputData log shiftToggle0
MBISTRESETNInputMBIST resetToggle0[a]
MBISTRESULT[2:0]OutputOutput status busStrobe-
MBISTRUNInputRun MBIST testToggle0
MBISTSHIFTInputInstruction shiftToggle0
MTESTONInputMBIST path enableToggle0[a]
SEInputATPG signal00

[a] Must be LOW in functional mode.


Note

nRESET of the cache controller must be HIGH in MBIST test mode.

The following signals have additional information:

SE

Preservation of array state is required when performing multiload Automatic Test Pattern Generator (ATPG) runs or when performing Integrated Circuit Quiescent Current (IDDQ) testing. After performing MBIST tests to initialize the arrays to a required background, the ATPG test procedures must assert SE during all test setup cycles in addition to load/unload. Any clocking during IDDQ capture cycles must have array chip select signals constrained.

MBISTRESULT[2:0]

During tests, the MBISTRESULT[1] signal indicates failures. You can operate using two modes, by configuring bit 5 of the engine control section of the instruction register. If bit 5 is set, the MBISTRESULT[1] signal is asserted for a single cycle for each failed compare. If bit 5 is not set, the MBISTRESULT[1] signal is sticky, and is asserted from the first failure until the end of the test.

At the completion of the test, the MBISTRESULT[2] signal goes HIGH. The MBISTRESULT[0] signal indicates that an address expire has occurred and enables you to measure sequential progress through the test algorithms.

Copyright © 2007-2010 ARM. All rights reserved.ARM DDI 0402E
Non-Confidential