3.2.1. Pattern field, MBIR[60:55]

The MBIST controller is supplied with industry-standard pattern algorithms and a bit-line stress algorithm. You can group algorithms together to create a specific memory test methodology for your product.

Table 3.1 describes the supported algorithms, and Pattern specification describes their use. The N values in the table indicate the number of RAM accesses per address location and give an indication of the test time when using that algorithm.

Table 3.1. Pattern field encoding

Pattern MBIR[60:55]

Algorithm nameNDescription
b000000Write Solids1NWrite a solid pattern to memory
b000001Read Solids1NRead a solid pattern from memory
b000010Write Checkerboard1NWrite a checkerboard pattern to memory
b000011Read Checkerboard1NRead a checkerboard pattern from memory
b000100March C+ (x-fast)14NMarch C+ algorithm, incrementing X-address first
b001011March C+ (y-fast)14NMarch C+ algorithm, incrementing Y-address first
b000101Fail Pattern6NTests memory failure detection capability
b000110Read Write March (x-fast)6NRead write march pattern, incrementing X-address first
b000111Read Write March (y-fast)6NRead write march pattern incrementing Y-address first
b001000Read Write Read March (x-fast)8NRead write read march pattern, incrementing X-address first
b001001Read Write Read March (y-fast)8NRead write read march pattern, incrementing Y-address first
b001010Bang18NBit-line stress pattern
b111111Go/No-Go30NSee Table 3.2

Pattern specification

This section describes the MBIST test patterns. An x-fast pattern increments or decrements the X-address counter first. A y-fast pattern increments or decrements the Y-address counter first. Y-address and X-address fields, MBIR[36:33] and MBIR[40:37] describes the X-address and Y-address counters.

The first four patterns are useful for data retention or IDDQ testing.

Write Solids

This initializes the RAM with the supplied data seed.

Read Solids

This reads each RAM location once expecting the supplied data seed.

Write Checkerboard

This initializes the RAM with a physical checkerboard pattern created by alternating the supplied data seed and its inverse.

Read Checkerboard

This reads back the physical checkerboard pattern created by alternating the supplied data seed and its inverse.

For the next set of patterns, the following notation describes the algorithm:

  • 0 represents the data seed

  • 1 represents the inverse data seed

  • w indicates a write operation

  • r indicates a read operation

  • incr indicates that the address is incremented

  • decr indicates that the address is decremented.

March C+ (x-fast or y-fast)

This is the industry-standard March C+ algorithm:

(w0) (r0, w1, r1) (r1, w0, r0) decr (r0, w1, r1) decr (r1, w0, r0) (r0)
Read Write March (x-fast or y-fast)
(w0) (r0, w1) decr (r1, w0) (r0)
Read Write Read March (x-fast or y-fast)
(w0) (r0, w1, r1) decr (r1, w0, r0) (r0)

This test is always performed in x-fast. It executes multiple consecutive writes and reads effectively stressing a bit-line pair. While this pattern does detect stuck-at faults, its primary intent is to address the analog characteristics of the memory. In the following algorithm description, row 0 indicates a read or write of the data seed to the sacrificial row, this is always the first row of the column being addressed.

(w0) (r0, w0, w0(row 0) × 6)  (r0 × 5, w0(row 0), r0) (r0)

If you do not want to implement your own memory test strategy, use the Go/No-Go test pattern that performs the algorithms that Table 3.2 shows.

Table 3.2. Go/No-Go test pattern

1Write CheckerboardData seed
2Read CheckerboardData seed
3Write CheckerboardData seed
4Read CheckerboardData seed
5Read Write Read March (y-fast)0x6

This test suite provides a comprehensive test of the arrays. The series of tests in Go/No-Go are the result of the experience in memory testing by ARM memory test engineers.

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