1.2. MBIST controller interface

Figure 1.2 shows the MBIST controller interface to the Automated Test Equipment (ATE) and to the MBIST interface of the cache controller.

Figure 1.2. MBIST controller wiring diagram


Figure 1.3 shows the traditional method of accessing a cache RAM for MBIST.

Figure 1.3. Traditional method of interfacing MBIST


Because this method significantly reduces the maximum operating frequency, it is not suitable for high-performance designs. Instead, the MBIST controller uses an additional input to the existing functional multiplexors without reducing maximum operating frequency.

Figure 1.4 shows the five pipeline stages used to access the cache RAM arrays.

Figure 1.4. Cache controller MBIST interface


The MBIST controller accesses memory through the MBIST interface of the cache controller. Table 1.1 lists the cache controller MBIST interface signals.

Table 1.1. Cache controller MBIST interface signals

NameTypeDescription
nRESETInputGlobal active LOW reset signal.
CLKInputActive HIGH clock signal. This clock drives the cache controller logic.
MBISTDOUT[63:0]Output

Data out bus from all cache RAM blocks.

MBISTDCTL[19:0]InputDelayed versions of the MBISTCE[17:0] signal and the doubleword select signal, MBISTADDR[1:0]. Selects the correct read data after it passes through the MBIST pipeline stages. MBISTDCTL[19:0] = delayed {MBISTCE[17:0]MBISTADDR[1:0]}.
MTESTONInput

Select signal for cache RAM array. This signal is the select input to the multiplexors that access the cache RAM arrays for test. When asserted, MTESTON takes priority over all other select inputs to the multiplexors.

MBISTCE[17:0]Input

One-hot chip enables to select cache RAM arrays for test.

MBISTWE[31:0]Input

Global write enable signal for all RAM arrays.

MBISTADDR[19:0]Input

Address signal for cache RAM array. MBISTADDR[1:0] is the doubleword select value. See Y-address and X-address fields, MBIR[36:33] and MBIR[40:37] for a description of the doubleword select. Not all RAM arrays use the full address width.

MBISTDIN[63:0]Input

Data bus to the cache RAM arrays. Not all RAM arrays use the full data width.


Note

The interface of the MBIST controller communicates with both the ATE and the MBIST interface of the cache controller. See Appendix A Signal Descriptions for descriptions of the MBIST controller interface signals. See the ARM AMBA Level 2 Cache Controller (L2C-310) Technical Reference Manual for more information about the MBIST interface.

Copyright © 2007-2010 ARM. All rights reserved.ARM DDI 0402E
Non-Confidential