CoreLink Level 2 MBIST Controller L2C-310 Technical Reference ManualRevision: r3p2
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CoreLink™ Level 2 MBIST Controller L2C-310 Technical Reference Manual

Revision: r3p2

Copyright © 2007-2010 ARM. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the MBIST controller
1.2. MBIST controller interface
1.3. RTL configuration
1.4. Product revisions
2. Functional Description
2.1. Functional overview
2.1.1. MBIST controller interface
2.1.2. MBIST controller implementation
2.2. Functional operation
2.2.1. Timing
2.2.2. Bitmap mode
3. MBIST Instruction Register
3.1. About the MBIST Instruction Register
3.2. Field descriptions
3.2.1. Pattern field, MBIR[60:55]
3.2.2. Control field, MBIR[54:49]
3.2.3. Read latency and write latency fields, MBIR[44:41] and MBIR[48:45]
3.2.4. Y-address and X-address fields, MBIR[36:33] and MBIR[40:37]
3.2.5. Data seed field, MBIR[32:29]
3.2.6. Enables field, MBIR[28:11]
3.2.7. Column width field, MBIR[10:9]
3.2.8. Cache size field, MBIR[8:6]
3.2.9. Way size field, MBIR[5:3]
3.2.10. Parity support field, MBIR[2]
3.2.11. Lockdown by line support field, MBIR[1]
3.2.12. Way configuration field, MBIR[0]
A. Signal Descriptions
A.1. MBIST controller interface signals
A.2. Miscellaneous signals
B. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Cache controller MBIST configuration without data banking
1.2. MBIST controller wiring diagram
1.3. Traditional method of interfacing MBIST
1.4. Cache controller MBIST interface
2.1. Cache controller MBIST and RAM interfaces
2.2. Cache controller compiled RAM latency
2.3. Cache controller MBIST paths for data RAM testing
2.4. Cache controller MBIST paths for tag RAM testing
2.5. MBIST controller block
2.6. Loading the MBIST controller instruction
2.7. Starting the MBIST test
2.8. Detecting an MBIST failure
2.9. Start of data log retrieval
2.10. End of data log retrieval
2.11. Start of bitmap data log retrieval
2.12. End of bitmap data log retrieval
3.1. MBIST Instruction Register
3.2. Example data RAM topology
3.3. MBIST address scrambling for normal mode
3.4. MBIST address scrambling for banked mode data and data parity RAM

List of Tables

1.1. Cache controller MBIST interface signals
2.1. Cache controller compiled RAM latency
2.2. MBISTADDR and MBISTDIN mapping for data RAM, 8-way
2.3. MBISTADDR and MBISTDIN mapping for data RAM, 16-way
2.4. Writes for data RAM testing
2.5. MBISTADDR and MBISTDIN mapping for tag RAM, 8-way
2.6. MBISTADDR and MBISTDIN mapping for tag RAM, 16-way
2.7. MBISTTX signals
2.8. MBISTRX signals
2.9. MBIST controller top level I/O
2.10. Data log format
3.1. Pattern field encoding
3.2. Go/No-Go test pattern
3.3. Control field encoding
3.4. Read latency field encoding
3.5. Write latency field encoding
3.6. Y-address field encoding
3.7. X-address field encoding
3.8. Required sums of X-address and Y-address fields for data RAM
3.9. Required sums of X-address and Y-address fields for tag RAM
3.10. Required sums of X-address and Y-address fields for data parity RAM
3.11. Enables field encoding
3.12. Column width field encoding
3.13. Cache size field encoding
3.14. Way size field encoding
A.1. MBIST controller interface signals
A.2. Miscellaneous signals
B.1. Differences between issue C and issue D
B.2. Differences between issue D and issue E
B.3. Differences between issue E and issue F

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A30 November 2007First release for r0p0
Revision B04 April 2008First release for r1p0
Revision C19 December 2008First release for r2p0
Revision D01 October 2009First release for r3p0
Revision E03 February 2010First release for r3p1
Revision F10 December 2010First release for r3p2
Copyright © 2007-2010 ARM. All rights reserved.ARM DDI 0402F
Non-ConfidentialID011711
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