2.3.6. AXI master interface clocking

The Cortex-A9 MPCore Bus Interface Unit supports the following AXI bus ratios:

These ratios are configured through external pins and system registers. In all cases AXI transfers remain synchronous. There is no requirement for an asynchronous AXI interface with integer and half integer ratios. To support this, the following signals qualify input and output signals on AXI:

Figure 2.9 shows input data going from a slave to a master with a timing ratio of two to three.

Figure 2.9. Input data from a slave to a master with a two-to-three ratio


Figure 2.10 shows input data going from a slave to a master with a timing ratio of two to five.

Figure 2.10. Input data from a slave to a master with a two-to-five ratio


Figure 2.11 shows output data going from a master to a slave with a timing ratio of two to three.

Figure 2.11. Output data from master to slave with a three-to-two ratio


Figure 2.12 shows output data going from a master to a slave with a timing ratio of two to five.

Figure 2.12. Output data from master to slave with a two-to-five ratio


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