A.4. Configuration signals

Table A.6 shows the configuration signals.

Table A.6. Configuration signals

NameI/O

Source or

destination

Description
CFGEND[N:0]ISystem configuration

Individual Cortex-A9 processor endianness configuration.

Forces the EE bit in the CP15 c1 Control Register (SCTLR) to 1 at reset so that the Cortex-A9 processor boots with big-endian data handling.

0 = EE bit is LOW

1 = EE bit is HIGH

This pin is only sampled during reset of the processor.

CFGNMFI[N:0]I

Individual Cortex-A9 processor configuration of fast interrupts to be nonmaskable:

0 = clear the NMFI bit in the CP15 c1 Control Register

1 = set the NMFI bit in the CP15 c1 Control Register.

This pin is only sampled during reset of the processor.

CLUSTERID[3:0]I

Value read in Cluster ID register field, bits[11:8] of the MPIDR.

FILTERENI

For use with configurations with two master ports. Enables filtering of address ranges at reset. See SCU Control Register for information on setting this signal.

FILTERSTART[31:20]IFor use with configurations with two master ports. Specifies the start address for address filtering at reset. See Filtering Start Address Register.
FILTEREND[31:20]IFor use with configurations with two master ports. Specifies the end address for address filtering. See Filtering End Address Register.
PERIPHBASE[31:13]I

Specifies the base address for Timers, Watchdogs, Interrupt Controller, and SCU registers. Only accessible with memory-mapped accesses. This value can be retrieved by a Cortex-A9 processor using the CP15 c15 Configuration Base Address Register.

SMPnAMP[N:0]OSystem integrity controller

Signals AMP or SMP mode for each Cortex-A9 processor.

0 = Asymmetric

1 = Symmetric.

TEINIT[N:0]ISystem configuration

Individual Cortex-A9 Processor out-of-reset default exception handling state. When set to:

0 = ARM

1 = Thumb.

This pin is only sampled during reset of the processor. It sets the initial value of SCTLR.TE.

VINITHI[N:0]I

Individual Cortex-A9 Processor control of the location of the exception vectors at reset:

0 = exception vectors start at address 0x00000000

1 = exception vectors start at address 0xFFFF0000.

This pin is only sampled during reset of the processor. It sets the initial value of SCTLR.V.


Table A.7 shows the security control signals.

Table A.7. Security control signals

NameI/O

Source or

destination

Description
CFGSDISABLEISecurity controller

Disables write access to some system control processor registers:

0 = not enabled

1 = enabled.

See Using CFGSDISABLE.

CP15SDISABLE[N:0]I

Individual Cortex-A9 Processor write access disable for some system control processor registers.


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