2.2.6. Filtering End Address Register

The Filtering End Address Register characteristics are:


Provides the end address for use with master port 1 in a two-master port configuration.

Usage constraints

This register is writable

  • in Secure state if the relevant bit in the SAC register is set.

  • in Non-secure state if the relevant bits in the SAC and SNSAC registers are set.

  • has an inclusive address as its end address. This means that the topmost megabyte of address space of memory can be included in the filtering address range.


Available in all two-master product configurations. When only one master port is present writes have no effect and reads return a value 0x0 for all filtering registers.


See the register summary in Table 2.1.

Figure 2.6 shows the Filtering End Address Register bit assignments.

Figure 2.6. Filtering End Address Register bit assignments

Table 2.7 shows the bit assignments for the Filtering End Address Register.

Table 2.7. Filtering End Address Register bit assignments

Bits Name Description
[31:20]Filtering end address

End address for use with master port 1 in a two-master port configuration, when address filtering is enabled.

The default value is the value of FILTEREND sampled on exit from reset. The value on the pin gives the upper address bits with 1MB granularity.


See Configuration signals .

Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0407E