A.2. Resets and reset control signals

Table A.2 shows the reset signals.

Table A.2. Reset signals

nCPURESET[N:0]IReset controller or clock controllerIndividual Cortex-A9 processor resets
nDBGRESET[N:0]IProcessor debug logic resets



Cortex-A9 MPE SIMD logic resets

nPERIPHRESETITimer and interrupt controller reset
nSCURESETISCU global reset
nWDRESET[N:0]IProcessor watchdog resets

[a] Only if an MPE is present

Table A.3 shows the clock control signals that are used to cut the clocks during reset sequences. NEONCLCKOFF is only present when there is a Data Engine in your design. See Chapter 5 Clocks, Resets, and Power Management.

Table A.3. Reset clock control signals

CPUCLKOFFIReset controller

Individual Cortex-A9 Processor CPU clock enable, active-LOW.

0 = clock is enabled

1 = clock is stopped.


IMPE SIMD logic clock control:0 = do not cut MPE SIMD logic clock1 = cut MPE SIMD logic clock.

Table A.4 shows the watchdog request reset signal.

Table A.4. Watchdog request reset signal

WDRESETREQ[N:0]OSystem exception controllerProcessor watchdog reset requests

See Chapter 4 Global timer, Private timers, and Watchdog registers.

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