2.2.2. SCU Configuration Register

The SCU Configuration Register characteristics are:

Purpose
  • read tag RAM sizes for the Cortex-A9 processors that are present

  • determine the Cortex-A9 processors that are taking part in coherency

  • read the number of Cortex-A9 processors present.

Usage constraints

This register is read-only.

Configurations

Available in all Cortex-A9 multiprocessor configurations.

Attributes

See the register summary in SCU registers.

Figure 2.2 shows the format for this register.

Figure 2.2. SCU Configuration Register bit assignments


Table 2.3 shows the SCU Configuration Register bit assignments.

Table 2.3. SCU Configuration Register bit assignments

BitsNameDescription
[31:16]ReservedShould-Be-Zero (SBZ).
[15:8] Tag RAM sizes

Bits [15:14] indicate Cortex-A9 processor CPU3 tag RAM size if present.

Bits [13:12] indicate Cortex-A9 processor CPU2 tag RAM size if present.

Bits [11:10] indicate Cortex-A9 processor CPU1 tag RAM size if present.

Bits [9:8] indicate Cortex-A9 processor CPU0 tag RAM size.

The encoding is as follows:

b11 = reserved

b10 = 64KB cache, 256 indexes per tag RAM

b01 = 32KB cache, 128 indexes per tag RAM

b00 = 16KB cache, 64 indexes per tag RAM.

[7:4]CPUs SMP

Defines the Cortex-A9 processors that are in Symmetric Multi-processing (SMP) or Asymmetric Multi-processing (AMP) mode.

0 = this Cortex-A9 processor is in AMP mode not taking part in coherency or not present.

1 = this Cortex-A9 processor is in SMP mode taking part in coherency.

Bit 7 is for CPU3

Bit 6 is for CPU2

Bit 5 is for CPU1

Bit 4 is for CPU0.

[3:2]ReservedSBZ
[1:0]CPU number

Number of CPUs present in the Cortex-A9 MPCore processor

b11 = four Cortex-A9 processors, CPU0, CPU1, CPU2, and CPU3

b10 = three Cortex-A9 processors, CPU0, CPU1, and CPU2

b01 = two Cortex-A9 processors, CPU0 and CPU1

b00 = one Cortex-A9 processor, CPU0.


Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0407E
Non-Confidential