2.2.4. SCU Invalidate All Registers in Secure State Register

The SCU Invalidate All Registers in Secure State characteristics are:

Purpose

Invalidates the SCU tag RAMs on a per Cortex-A9 processor and per way basis.

Usage constraints

This register:

  • Invalidates all lines in the selected ways.

  • Is writable in Secure state if the relevant bit in the SAC register is set.

Configurations

Available in all Cortex-A9 multiprocessor configurations.

Attributes

See the register summary in Table 2.1.

Figure 2.4 shows the format of this register.

Figure 2.4. SCU Invalidate All Registers in Secure state bit assignments


Table 2.5 shows the SCU Invalidate All Register in Secure state bit assignments.

Table 2.5. SCU Invalidate All Registers in Secure state bit assignments

BitsNameDescription
[31:16]--
[15:12]CPU3 waysIndicates the ways that must be invalidated for Cortex-A9 MPCore CPU3. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than four processors.
[11:8]CPU2 waysIndicates the ways that must be invalidated for Cortex-A9 MPCore CPU2. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than three processors.
[7:4]CPU1 waysIndicates the ways that must be invalidated for Cortex-A9 MPCore CPU1. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than two processors.
[3:0]CPU0 waysIndicates the ways that must be invalidated for Cortex-A9 MPCore CPU0.

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