A.13.2. APB interface signals

Table A.31 shows the APB interface signals.

Table A.31. APB interface signals

NameI/O

Source or

destination

Description
PADDRDBG[x:2]ICoreSight APB device

Programming address. The width of x:2 depends on the configuration:

[12:2] A uniprocessor or multiprocessor configuration with a single Cortex-A9 processor

[13:2] A multiprocessor configuration with two Cortex-A9 processors

[14:2] A multiprocessor configuration with three or four Cortex-A9 processors.

PADDRDBG31I

APB address bus bit [31]:

0 = not an external debugger access

1 = external debugger access

PENABLEDBGIIndicates a second and subsequent cycle of a transfer.
PSELDBGI

Selects the external debug interface:

0 = debug registers not selected

1 = debug registers selected.

PWDATADBG[31:0]IWrite data bus.
PWRITEDBGIAPB read and write signal.
PRDATADBG[31:0]ORead data bus
PREADYDBGO

Used to extend a transfer by inserting wait states

APB slave ready. An APB slave can assert PREADY to extend a transfer.

PSLVERRDBGO

APB slave transfer error:

0 = no transfer error

1 = transfer error.


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