Appendix B. Revisions

This appendix describes the technical changes between released issues of this books.

Table B.1. Issue A

ChangeLocation
First release-

Table B.2. Differences between issue A and issue B

ChangeLocation
Clarify the relationship between the GIC (PL390) and the Cortex-A9 Interrupt Controller

Chapter 3 Interrupt Controller.

Parity error option addedTable 1.1.
Clarify the role of the SCU with reference to data coherency and the non-support of instruction cache coherencyAbout the SCU.
Added information about exclusive accesses and address filteringAddress filtering on page 2-2.
SSAC description corrected

SCU Non-secure Access Control Register.

SSAC bit assignments correctedTable 2.9.
Change STI, Software Triggered Interrupt, to SGI, Software Generated Interrupt

Throughout Chapter 3 Interrupt Controller.

INTID descriptions extended and clarified

Throughout Chapter 3 Interrupt Controller.

Reset information added

Timer and watchdog registers on page 5-3.

AXI transaction IDs section extended

AXI transaction IDs on page 6-3.

AXI USER encodings section added

AXI USER encodings on page 6-5.

EVENTI information extended and EVENTO information addedWFE/SEV synchronization on page 6-9.

CLUSTERID[3:0] description corrected

Configuration signals .
DBGEN[3:0] description added

Table A.30.


Differences between issue B and issue C

Table B.3. Differences between issue B and issue C

ChangeLocation
Design changes listed Product revisions.
New entries in the Private Memory mapTable 2-2 on page 2-3.
Timers and watchdogs renamed Private timers and watchdogsTable 2-2 on page 2-3.
TLB size added as a configurable optionTable 1.1.
Timing diagrams addedFigure 1-4 on page 1-25, Figure 1-5 on page 1-25, Figure 1-6 on page 1-26, and Figure 1-7 on page 1-26.
CPUCLKOFF and DECLKOFF added to Power-on resetCortex-A9 MPCore reset on page 1-28. Configuration signals .
Change in SCU Power Status Register layoutSCU CPU Power Status Register on page 2-7
Additional PPI. There are five PPIs per Cortex-A9 processor interfaceInterrupt types and sources.
PPI(4) added to the PPI Status RegisterPPI Status Register.
INT renamed IRQSSPI Status Registers. Interrupts.
Chapter 5 renamed. It was “Private timers and Watchdog Registers”.Chapter 4 Global timer, Private timers, and Watchdog registers.
L2 interface chapter included in Chapter 1 
nIRQOUT[N:0] and nFIQOUT[N:0] addedInterrupts.
MAXCLKLATENCY[2:0] addedConfiguration signals .
BISTCLAMP removedPower management signals.
AXI descriptions corrected and extendedAXI interfaces.
AXI Master1 descriptions removed.
AWLOCKS[1:0] corrected to AWLOCKS[0].Table A.17.
ARIDS[5:0] corrected to ARIDS[2:0].Table A.20.
Performance monitoring signals extended and new signals added.Performance monitoring signals.
SCUEVABORT moved to Performance Monitoring from Parity error signals section.Performance monitoring signals.
SCANMODE removedScan test signal.
PRDATADBG corrected to PRDATADBG[31:0]Table A.31.
WPTT32nT16n changed to WPT32LINKnTable A.34.

Differences between issue C and issue D.

Table B.4. Differences between issue C and issue D

ChangeLocation
ARM Architecture Reference Manual promoted to head of ARM publicationsARM publications
Global timer re-positioned. Other timers re-named private timers.Figure 1.1
Compliance content moved and extendedAbout Cortex-A9 MPCore coherency
Features list removed 
Configurable options includes Preload Engine options and ARM_BISTConfigurable options
Interfaces section extendedInterfaces
Private Memory Region chapter removed 
Private Memory Region content re-arranged. Table addedPrivate Memory Region
SLVERR changed to DECERRTable 1.2
Interfaces section extendedInterfaces
MPCore Considerations section addedMPCore considerations
ACP behavior description moved and extendedAccelerator Coherency Port
Design changes list extended Product revisions.
Snoop Control Unit chapter updated and extended to include detailed interface descriptionsChapter 2 Snoop Control Unit
SCU Register updatesTable 2.1
Interfaces SCU Control Register
Removal of content that repeats GIC Architecture contentChapter 3 Interrupt Controller
Re-organization of remaining Interrupt Controller content 
Timer control register descriptions extendedPrivate Timer Control Register
Section addedGlobal Timer Control Register
Resets descriptions revised and extendedResets
Signals lists updatedSource or destination column added to all signal lists
nNEONRESET[N:0] replaces nDERESET[N:0]Table A-2
NEONCLCKOFF replaces DECLCKOFFTable A.6
CPUCLCKOFF[N:0] replaces CPUCLOCKOFF[N:0]
CP15 c15 Configuration Base Address Register replaces System Control Configbase Register
NEONCLAMP replaces DECLAMPTable A.9
Power control signal descriptions corrected and clarified.
SCUIDLE signal added
Duplicated AXI user encodings removedTable A.10
ARUSERM0[6:0] correctedTable A.13

Speculative read interface signals section added

Speculative read interface signals for M0
[4:0] in AWUSERS[4:0] corrected to [4:1]Table A.17
NEON SIMD unit replaces MPETable A.23

PMUEVENT size become 57 bits

DEFLAGS and SCUEVABORT have a separate tableException flags signals
PARITYSCU[3:0] becomes PARITYFAILSCU[N:0]Table A.25
MBISTBE[31:0] becomes MBISTBE[32:0]Table A.27
Description of DBGSWENABLE[N:0] amendedTable A.33
DBGSELFADDR bits corrected to [31:15]
WPTCOMMITn bits corrected to [1:0]Table A.34
WPTENABLE corrected to WPTENABLEn
WPT32LINKn corrected toWPTT32LINKn
Statement about WPTTARGETTBIT removed

Table B.5. Differences between Issue D and Issue E

ChangeLocation
No technical change-

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