3.4.1. Processor Interface Implementer Identification Register

The ICPIIR Register characteristics are:


Provides information about the implementer and the revision of the controller.

Usage constraints

There are no usage constraints.


Available in all Cortex-A9 multiprocessor configurations.


See the register summary in Table 3.20.

Figure 3.13 shows the ICPIIR Register bit assignments.

Figure 3.13. ICPIIR Register bit assignments

Table 3.21 shows the ICPIIR Register bit assignments.ss

Table 3.21. ICPIIR Register bit assignments

[31:20]Part number

Identifies the peripheral.

[19:16]Architecture version

Identifies the architecture version.

[15:12]Revision number

Returns the revision number of the Interrupt Controller. The implementer defines the format of this field.


Returns the JEP106 code of the company that implemented the Cortex-A9 processor interface RTL. It uses the following construct:


the JEP106 continuation code of the implementer




the JEP106 code [6:0] of the implementer.

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