2.3.3. AXI transaction IDs

There are several possible sources for the AXI transactions a Cortex-A9MP processor issues on its AXI master ports. This section describes the AXI transaction IDs and AXI USER bits in the following sections:

ARIDMx[5:0] encodings

This section describes the ARIDMx[5:0] encodings for read transactions. As Table 2.11 shows, the ARIDMx[2] encodings distinguish between transactions originating from Cortex-A9 processors and transactions originating from the ACP:

  • ARIDMx[2] = 0 the transaction originates from one of the Cortex-A9 processors.

  • ARIDMx[2] = 1 the transaction originates from the ACP.

Table 2.11. ARID encodings

 Transaction types
 Cortex-A9 transactionsACP transactions

ARIDMx[2]

ARIDMx[2] = 0

ARIDMx[2] = 1

ARIDMx[5:3]

Transaction type:

b000 non-cacheable

b010 data linefill buffer 0

b011 data linefill buffer 0

b100 instruction linefill

b101 instruction linefill

b110 instruction linefill

b111 instruction linefill

ACP read IDs

ARIDMx[5:3] = ARIDS[2:0]

ARIDMx[1:0]

Cortex-A9 processor:

b00 CPU0

b01 CPU1

b10 CPU2

b11 CPU3

Unused

AWIDMx[5:0] encodings

This section describes the AWIDMx[5:0] encodings for write transactions. As Table 2.12 shows, the AWIDMx[2] encodings distinguish between transactions originating from Cortex-A9 processors and transactions originating from the ACP:

  • AWIDMx[2] = 0 the transaction originates from one of the Cortex-A9 processors.

  • AWIDMx[2] = 1 the transaction originates from the ACP.

Table 2.12. AWIDMx encodings

 Transaction types
 Cortex-A9 transactionsACP transactions

AWIDMx[2]

AWIDMx[2] = 0

AWIDMx[2] = 1

AWIDMx[5:3]

b000 non-cacheable

b010 eviction

b011 eviction

b100 eviction

b101 eviction

ACP read IDs

AWIDMx[5:3] = AWIDS[2:0]

AWIDMx[1:0]

b00 CPU0

b01 CPU1

b10 CPU2

b11 CPU3

Unused, forced to b00>

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