3.3.7. PPI Status Register

The ppi_status Register characteristics are:

Purpose

Enables a Cortex-A9 processor to access the status of the private inputs on the distributor:

  • PPI(4) is for nIRQ<n>

  • PPI(3) is for watchdog interrupts

  • PPI(2) is for private timer interrupts

  • PPI(1) is for nFIQ<n>

  • PPI(0) is for the global timer.

Usage constraints

A Cortex-A9 processor can only read the status of its own PPI and therefore cannot read the status of PPI for other Cortex-A9 processors.

Configurations

Available in all Cortex-A9 multiprocessor configurations.

Attributes

See the register summary in Table 3.1.

Figure 3.7 shows the ppi_status Register bit assignments.

Figure 3.7. ppi_status Register bit assignments


Table 3.6 shows the register bit assignments.

Table 3.6. ppi_status Register bit assignments

BitsNameDescription
[31:16]-

Reserved

[15:11]

ppi_status

Returns the status of the PPI(4:0) inputs on the distributor:

  • PPI[4] is nIRQ

  • PPI[3] is the private watchdog

  • PPI[2] is the private timer

  • PPI[1] is nFIQ

  • PPI[0] is the global timer.

PPI[1] and PPI[4] are active LOW

PPI[0], PPI[2] and PPI[3] are active HIGH.

Note

These bits return the actual status of the PPI(4:0) signals. The pending_set and pending_clr Registers also can provide the PPI(4:0) status but because you can write to these registers then they might not contain the actual status of the PPI(4:0) signals.

[10:0]-SBZ

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