An ACP read request is coherent when ARUSER[0] = 1 and ARCACHE[1] = 1 alongside ARVALID.

In this case, the SCU enforces coherency.

When the data is present in one of the Cortex-A9 processors within the Cortex-A9MPCore, the data is read directly from the relevant processor, and returned to the ACP port.

When the data is not present in any of the Cortex-A9 processors, the read request is issued on one of the Cortex-A9 MPCore AXI master ports, along with all its AXI parameters, with the exception of the locked attribute.

An ACP read request is non-coherent when ARUSER[0] = 0 or ARCACHE[1] =0 alongside ARVALID.

In this case, the SCU does not enforces coherency, and the read request is directly forwarded to one of the available Cortex-A9 MPCore AXI master ports.

An ACP write request is coherent when AWUSER[0] = 1 and AWCACHE[1] =1 alongside AWVALID.

In this case, the SCU enforces coherency.

When the data is present in one of the Cortex-A9 processors within the Cortex-A9 MPCore, the data is first cleaned and invalidated from the relevant CPU.

When the data is not present in any of the Cortex-A9 processors, or once it has been cleaned and invalidated, the write request is issued on one of the Cortex-A9 MPCore AXI master ports, along with all corresponding AXI parameters with the exception of the locked attribute.

An ACP write request is non-coherent when AWUSER[0] = 1 or AWCACHE[1] = 0 alongside AWVALID.

In this case, the SCU does not enforce coherency, and the write request is forwarded directly to one of the available Cortex-A9 MPCore AXI master ports.