5.3.2. Communication to the Power Management Controller

Communication between the Cortex-A9 processor and the external Power Management Controller can be performed using the PWRCTLOn Cortex-A9 MPCore output signals and Cortex-A9 MPCore input clamp signals.

PWRCTLOn Cortex-A9 MPCore output signals

These signals constrain the external Power Management Controller. The value of PWRCTLOn depends on the value of the SCU CPU Status Register (see SCU CPU Power Status Register). The SCU CPU Status Register value is only copied to PWRCTLOn after the Cortex-A9 processor signals that it is ready to enter low power mode by executing a WFI instruction and subsequent STANDBYWFI pin assertion.

Cortex-A9 MPCore input signals

The external Power Management Controller uses DEBUGCLAMP, CPUCLAMP[3:0], DECLAMP[3:0], and RAMCLAMP[4:0] to isolate Cortex-A9 MPCore power domains from one another before they are turned off. These signals are only meaningful if the Cortex-A9 MPCore processor has been implemented with power clamps designed in.

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