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The periph_id_[4:0] Registers provide information about the configuration of the peripheral. Table 3.1 shows the address base offset, reset value, and access type for these registers.
Each register provides eight bits of data but because some fields span across two adjacent periph_id registers then the following sections describe them:
Figure 3.10 shows the periph_id_[3:0] register group bit assignments.
Table 3.8 shows the periph_id_[3:0] register group bit assignments.
Table 3.8. periph_id_[3:0] Register bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:28] | RevAnd | These bits read as 0x0. |
| [27:24] | mod_number | Identifies data that is relevant to the ARM partner. |
| [23:20] | Architecture number | Identifies the major revision number,
r |
| [19] | jedec_used | Identifies if the IC uses the JEP106 manufacturer’s identity code. |
| [18:12] | JEP106[6:0] | Identifies the designer. This is set to b0111011, to indicate that ARM designed the peripheral. |
| [11:0] | part_number | Identifies the peripheral. |
The following subsections describe the periph_id_[3:0] registers:
The periph_id_0 Register is hard-coded and the fields in the register control the reset value. Table 3.9 shows the register bit assignments.
Table 3.9. periph_id_0 Register bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:8] | - | Reserved, read undefined |
| [7:0] | part_number_0 | - |
The periph_id_1 Register is hard-coded and the fields in the register control the reset value. Table 3.10 shows the register bit assignments.
Table 3.10. periph_id_1 Register bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:8] | - | Reserved, read undefined. |
[7:4] | jep106_id_3_0 | JEP106 identity code [3:0]. See the JEP106, Standard Manufacturer’s Identification Code. |
| [3:0] | part_number_1 | - |
The periph_id_2 Register is hard-coded and the fields in the register control the reset value. Table 3.11 shows the register bit assignments.
Table 3.11. periph_id_2 Register bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:8] | - | Reserved, read undefined. |
[7:4] | Architecture number | The architecture number of the IC. |
[3] | jedec_used | This indicates that the IC uses a manufacturer’s identity code that was allocated by JEDEC according to JEP106. |
[2:0] | jep106_id_6_4 | JEP106 identity code [6:4]. See the JEP106, Standard Manufacturer’s Identification Code. |
The periph_id_3 Register is hard-coded and the fields in the register control the reset value. Table 3.12 shows the register bit assignments.
Table 3.12. periph_id_3 Register bit assignments
Bits | Name | Description |
|---|---|---|
[31:8] | - | Undefined. |
[7:4] | RevAnd | - |
[3:0] | mod_number | The customer can update this field if they modify the RTL of the Interrupt Controller. |
Figure 3.11 shows the periph_id_[7:4] register group bit assignments.
Table 3.13 shows the periph_id_[7:4] register group bit assignments.
Table 3.13. periph_id_[7:4] Register bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:8] | - | - |
[7:4] | 4KB count | Identifies the address space that the registers occupy. |
[3:0] | jep106_c_code | Identifies the JEP106 continuation code. |
The following subsection describe the periph_id_[7:4] register:
The periph_id_4 Register is hard-coded and the fields in the register control the reset value. Table 3.14 shows the register bit assignments.
Table 3.14. periph_id_4 Register bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:8] | - | Undefined. |
[7:4] | 4KB count | The number of 4KB address blocks you require, to access the registers, expressed in powers of 2. |
[3:0] | jep106_c_code | The JEP106 continuation code value represents
how many |