Cortex-A9 MPCore Technical Reference Manual: A.11. MBIST interface

A.11. MBIST interface

Table A.26 shows the MBIST interface signals.

Table A.26. MBIST interface signals

Name	I/O	Source	Description
MBISTADDR[10:0]	I	MBIST controller	MBIST address.
MBISTARRAY[19:0]	I		MBIST arrays used for testing RAMs.
MBISTENABLE	I		Activates MBIST mode.
MBISTWRITEEN	I		Global write enable.
MBISTREADEN	I		Global read enable.

The size of some MBIST signals depends on whether the implementation has parity support or not. Table A.27 shows these signals with parity support implemented.

Table A.27. MBIST signals with parity support implemented

Name	I/O	Source or destination	Description
MBISTBE[32:0]	I	MBIST controller	MBIST write enable.
MBISTINDATA[71:0]	I	MBIST data in.
MBISTOUTDATA[287:0]	O	MBIST data out.

Name

I/O

Source or

destination

Description

MBISTBE[32:0]

MBIST controller

MBIST write enable.

MBISTINDATA[71:0]

MBIST data in.

MBISTOUTDATA[287:0]

MBIST data out.

Table A.28 shows these signals without parity support implemented.

Table A.28. MBIST signals without parity support implemented

Name	I/O	Source or destination	Description
MBISTBE[25:0]	I	MBIST controller	MBIST write enable.
MBISTINDATA[63:0]	I		MBIST data in.
MBISTOUTDATA[255:0]	O		MBIST data out.

See Cortex-A9 MBIST Controller TRM.

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