A.11. MBIST interface

Table A.26 shows the MBIST interface signals.

Table A.26. MBIST interface signals

NameI/O

Source

Description
MBISTADDR[10:0]IMBIST controllerMBIST address.
MBISTARRAY[19:0]IMBIST arrays used for testing RAMs.
MBISTENABLEIActivates MBIST mode.
MBISTWRITEENIGlobal write enable.
MBISTREADENIGlobal read enable.

The size of some MBIST signals depends on whether the implementation has parity support or not. Table A.27 shows these signals with parity support implemented.

Table A.27. MBIST signals with parity support implemented

NameI/O

Source or

destination

Description
MBISTBE[32:0]IMBIST controllerMBIST write enable.
MBISTINDATA[71:0]IMBIST data in.
MBISTOUTDATA[287:0]OMBIST data out.

Table A.28 shows these signals without parity support implemented.

Table A.28. MBIST signals without parity support implemented

NameI/O

Source or destination

Description
MBISTBE[25:0]IMBIST controllerMBIST write enable.
MBISTINDATA[63:0]IMBIST data in.
MBISTOUTDATA[255:0]OMBIST data out.

See Cortex-A9 MBIST Controller TRM.

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