A.3. Interrupts

Table A.5 shows the interrupt line signals.

Table A.5. Interrupt line signals

NameI/O

Source

Description
IRQS[x:0][a]IInterrupt sources

Interrupt distributor interrupt lines.

x can be 31, 63,…, up to 223 by increments of 32. If there are no interrupt lines this pin is removed.

See Chapter 3 Interrupt Controller.

nIRQ[N:0]aI

Individual Cortex-A9 processor legacy IRQ request input lines.

Active-LOW interrupt request:

0 = activate interrupt

1 = do not activate interrupt.

The processor treats the nIRQ input as level sensitive. The nIRQ input must be asserted until the processor acknowledges the interrupt.

nFIQ[N:0]aI

Individual Cortex-A9 processor private FIQ request input lines.

Active-LOW fast interrupt request:

0 = activate fast interrupt

1 = do not activate fast interrupt.

The processor treats the nFIQ input as level sensitive. The nFIQ input must be asserted until the processor acknowledges the interrupt.

nIRQOUT[N:0]OPower controller

Active-LOW output of individual processor nIRQ from the Interrupt Controller. For use when processors are powered off and interrupts are handled by the Interrupt Controller under the control of an external power controller.

nFIQOUT[N:0]O

Active-LOW output of individual processor nFIQ from the Interrupt Controller. For use when processors are powered off and interrupts are handled by the Interrupt Controller under the control of an external power controller.

[a] The minimum pulse width of signals driving external interrupt lines is one PERIPHCLK cycle.


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