CPUCLAMP[N:0]

Interrupt interface clamps control signals:

CPUCLAMP[3] CPU3 interface

CPUCLAMP[2] CPU2 interface

CPUCLAMP[1] CPU1 interface

CPUCLAMP[0] CPU0 interface.

CPURAMCLAMP[N:0]

Enables the clamp cells in Dormant mode.

SCURAMCLAMP

Enables the SCU clamp cells in Dormant mode.

NEONCLAMP[N:0]^[a]

Activates the Cortex-A9 MPE SIMD logic clamps:0 = clamps not active1 = clamps active..

Reset value for CPU0 status field (bits [1:0]) of SCU CPU Power Status Register[1:0].

Reset value for CPU0 status field (bits [9:8]) of SCU CPU Power Status Register.

[9:8].

Reset value for CPU0 status field (bits [17:16]) of SCU CPU Power Status Register.

[17:16].

Reset value for CPU0 status field (bits [25:24]) of SCU CPU Power Status Register.

[25:24].

b0x CPU0 must be powered on

b10 CPU0 can enter dormant mode

b11 CPU0 can enter powered-off mode.

b0x CPU1 must be powered on

b10 CPU1 can enter dormant mode

b11 CPU1 can enter powered-off mode.

This signal exists only if CPU1 is present.

b0x CPU2 must be powered on

b10 CPU2 can enter dormant mode

b11 CPU2 can enter powered-off mode.

This signal exists only if CPU2 is present.

b0x CPU3 must be powered on

b10 CPU3 can enter dormant mode

b11 CPU3 can enter powered-off mode

This signal exists only if CPU3 is present.

Indicates that the SCU is in IDLE state. This signal can be used to control clock or power-gating control signals of the modules connected to the SCU.

In the case of the PL310, the SCUIDLE output of the Cortex-A9 MPCore can be connected to the STOPCLK input of the PL310.