4.2.7. Watchdog Control Register

Figure 4.3 shows the Watchdog Control Register bit assignments.

Figure 4.3. Watchdog Control Register bit assignments


Table 4.3 shows the Watchdog Control Register bit assignments.

Table 4.3. Watchdog Control Register bit assignments 

BitsNameDescription
[31:16]-

Reserved.

[15:8]Prescaler

The prescaler modifies the clock period for the decrementing event for the Counter Register. See Calculating timer intervals.

[7:4]-

Reserved.

[3]Watchdog mode

1'b0 = Timer mode, default

Writing a zero to this bit has no effect. You must use the Watchdog Disable Register to put the watchdog into timer mode. See Watchdog Disable Register.

1'b1 = Watchdog mode.

[2]IT Enable

If set, the interrupt ID 30 is set as pending in the Interrupt Distributor when the event flag is set in the watchdog Status Register.

In watchdog mode this bit is ignored.

[1]Auto-reload

1'b0 = Single shot mode.

Counter decrements down to zero, sets the event flag and stops.

1'b1 = Auto-reload mode.

Each time the Counter Register reaches zero, it is reloaded with the value contained in the Load Register and then continues decrementing.

[0]Watchdog Enable

Global watchdog enable

1'b0 = Watchdog is disabled and the counter does not decrement. All registers can still be read and /or written

1'b1 = Watchdog is enabled and the counter decrements normally.


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