4.2.4. Private Timer Interrupt Status Register

Figure 4.2 shows the Private Timer Interrupt Status Register bit assignment.

This is a banked register for all Cortex-A9 processors present.

The event flag is a sticky bit that is automatically set when the Counter Register reaches zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1.

Figure 4.2. Private Timer Interrupt Status Register bit assignment


Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0407E
Non-Confidential