1.6.2. Differences in functionality between r1p0 and r0p1

These differences are in addition to the differences described in the Cortex-A9 TRM.

In r1p0 there is a global timer. See About the Global Timer.

In the Interrupt Controller INT becomes IRQS. See SPI Status Registers.

SCU CPU Power Status Register bits reassigned. See SCU CPU Power Status Register.

Copyright © 2008-2009 ARM. All rights reserved.ARM DDI 0407E
Non-Confidential