A.7.3. AXI ACP signals

The following sections describe the AXI ACP interface signals:

Write address signals for AXI ACP

Table A.17 shows the AXI write address signals for AXI ACP.

Table A.17. Write address signals for AXI ACP

NameI/O

Source or

destination

Description
AWADDRS[31:0]IExternal AXI masterAddress.
AWBURSTS[1:0]I

Burst type.

AWCACHES[3:0]I

Cache type giving additional information about cacheable characteristics.

AWIDS[2:0]IRequest ID
AWLENS[3:0]I

The number of data transfers that can occur within each burst.

AWLOCKS[0]I

Lock type:

b00 = normal access

b01 = exclusive access.

Bit [1] is unused. Tie off LOW.

AWPROTS[2:0]I

Protection Type.

AWREADYSOAddress ready.
AWSIZES[1:0]IExternal AXI master

Burst size:

b00 = 8-bit transfer

b01 = 16-bit transfer

b10 = 32-bit transfer

b11 = 64-bit transfer.

AWUSERS[4:0]I

Sideband information:

[4:1] inner attributes:

b0000 = Strongly-ordered

b0001 = Device

b0011 = Normal Memory Non-Cacheable

b0110 = Write-Through

b0111 = Write-Back no Write Allocate

b1111 = Write-Back Write Allocate

[0] shared.

See AXI USER attributes encodings.

AWVALIDSIAddress valid.

Write data channel signals

Table A.18 shows the AXI write data signals for AXI ACP.

Table A.18. Write data signals for AXI ACP

NameI/O

Source or

destination

Description
WDATAS[63:0]IExternal AXI masterWrite data
WIDS[2:0]IWrite ID
WLASTSIWrite last indication
WREADYSOWrite ready
WSTRBS[7:0]IWrite byte lane strobe
WVALIDSIWrite valid

Write response channel signals

Table A.19 shows the AXI write response signals for AXI ACP.

Table A.19. Write response signals for AXI ACP

NameI/O

Source or

destination

Description
BIDS[2:0]OExternal AXI masterResponse ID
BREADYSIResponse ready
BRESPS[1:0]OWrite response
BVALIDSOResponse valid

Read address channel signals

Table A.20 shows the AXI read address signals for AXI ACP.

Table A.20. Read address signals for AXI ACP

NameI/O

Source or

destination

Description
ARADDRS[31:0]IExternal AXI masterAddress.
ARBURSTS[1:0]I

Burst type.

ARCACHES[3:0]I

Cache type giving additional information about cacheable characteristics.

ARIDS[2:0]IRequest ID
ARLENS[3:0]I

The number of data transfers that can occur within each burst.

ARLOCKS[1:0]IExternal AXI master

Lock type.

ARPROTS[2:0]I

Protection Type

ARREADYSOAddress ready
ARSIZES[1:0]I

Burst size:

b00 = 8-bit transfer

b01 = 16-bit transfer

b10 = 32-bit transfer

b11 = 64-bit transfer.

ARUSERS[4:0]I

Sideband information:

[4:1] Inner attribute bits:

b0000 = Strongly-ordered

b0001 = Device

b0011 = Normal Memory Non-Cacheable

b0110 = Write-Through

b0111 = Write-Back no Write Allocate

b1111 = Write-Back Write Allocate.

[0] shared bit.

See AXI USER attributes encodings.

ARVALIDSIAddress valid.

Read data channel signals

Table A.21 shows the AXI read data signals for AXI ACP.

Table A.21. Read data signals for AXI ACP

NameI/O

Source or

destination

Description
RVALIDSOExternal AXI masterRead valid
RDATAS[63:0]ORead data
RRESPS[1:0]ORead response
RLASTSORead Last indication
RIDS[2:0]ORead ID
RREADYSIRead ready

Clock enable slave signal

Table A.22 shows the ACLKENS signal.

Table A.22. ACLKENS signal

NameI/O

Source or

destination

Description
ACLKENSIClock controller

Bus clock enable. See ACP interface clocking.


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