2.3.7. AXI master interface clocking

The Cortex-A9 MPCore Bus Interface Unit supports the following AXI bus ratios relative to CLK:

In all cases AXI transfers remain synchronous. There is no requirement for an asynchronous AXI interface with integer and half integer ratios. The ratios are configured through external pins, with the following signals that qualify the input and output signals on AXI:

Figure 2.9 shows a timing diagram example of read data return from an AXI slave back into the Cortex-A9 MPCore processor, with a three-to-two clock timing ratio.

Figure 2.9. Timing diagram for INCLKEN with three-to-two clock ratio between CPU and AXI Slave CLK

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Figure 2.10 shows a timing diagram example of read data return from an AXI slave back into the Cortex-A9 MPCore processor, with a five-to-two clock timing ratio.

Figure 2.10. Timing diagram for INCLKEN with five-to-two clock ratio between CPU and AXI Slave CLK

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Figure 2.11 shows a timing diagram example of data write from the Cortex-A9 MPCore processor into an AXI slave, with a three-to-two clock timing ratio.

Figure 2.11. Timing diagram for OUTCLKEN with three-to-two clock ratio between CPU and AXI Slave CLK

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Figure 2.12 shows a timing diagram example of data write from the Cortex-A9 MPCore processor into an AXI slave, with a five-to-two clock timing ratio.

Figure 2.12. Timing diagram for OUTCLKEN with five-to-two clock ratio between CPU and AXI Slave CLK

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