2.4.3. ACP limitations

The ACP is optimized for cache-line length transfers and it supports a wide range of AMBA 3 AXI requests, but it has some limitations that must be considered. This section describes some ACP limitations. It contains the following sections:

ACP performance limitations

ACP accesses are optimized for transfers that match Cortex-A9 processors coherent requests:

  • A wrapped burst of four doublewords (length = 3, size = 3), with a 64-bit aligned address, and all byte strobes set.

  • An incremental burst of four doublewords, with the first address corresponding to the start of a cache line, and all byte strobes set.

For maximum performance use ACP accesses that match this optimized format. ACP accesses that do not match this format cannot benefit from the SCU optimizations, and have significantly lower performance.

ACP functional limitations

The ACP is a full AMBA 3 AXI slave component, with the exception of the following transfers that are not supported:

  • Exclusive read and write transactions to coherent memory

  • All locked transactions, except SWP style transactions to non-coherent memory regions. An SWP style transaction is a locked read access to non-coherent memory, followed by a write access to the same address, and with the same attributes.

  • Optimized coherent read and write transfers when byte strobes are not all set.

As a consequence, it is not possible to use the LDREX/STREX mechanism through the ACP to gain exclusive access to coherent memory regions, that are marked with AxUSER[0] = 1 and AxCACHE[1] = 1.

However, the LDREX/STREX mechanism is fully supported through the ACP for non-coherent memory regions, marked with AxUSER[0] = 0 or AxCACHE[1] =0.

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