2.2.8. SCU Non-secure Access Control Register

The SNSAC register characteristics are:

Purpose

Controls Non-secure access to the following registers on a per Cortex-A9 processor basis:

In addition it controls Non-secure access to the global timer, private timers, and watchdog.

Usage constraints
  • This register is writable in Secure state if the relevant bit in the SAC register is set.

Configurations

Available in all Cortex-A9 multiprocessor configurations.

Attributes

See the register summary in Table 2.1.

Figure 2.8 shows the SNSAC register bit assignments.

Figure 2.8. SNSAC register bit assignments

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Table 2.9 shows the SNSAC register bit assignments.

Table 2.9. SNSAC register bit assignments

Bits NameFunction
[31:12]SBZ-
[11]CPU3 global timer

Non-secure access to the global timer for CPU<n>.

  • <n> is 3 for bit[11]

  • <n> is 2 for bit[10]

  • <n> is 1 for bit[9]

  • <n> is 0 for bit[8].

0 = Secure accesses only. This is the default value.

1 = Secure accesses and Non-Secure accesses.

[10]CPU2 global timer
[9]CPU1 global timer
[8]CPU0 global timer
[7]Private timers for CPU<n>

Non-secure access to the private timer and watchdog for CPU<n>.

  • <n> is 3 for bit[7]

  • <n> is 2 for bit[6]]

  • <n> is 1 for bit[5]

  • <n> is 0 for bit[4].

0 = Secure accesses only. Non-secure reads return 0. This is the default value.

1 = Secure accesses and Non-secure accesses.

[6]
[5]
[4]
[3]Register access for CPU<n>

Non-secure access to the registers for CPU<n>.

  • <n> is 3 for bit[3]

  • <n> is 2 for bit[2]]

  • <n> is 1 for bit[1]

  • <n> is 0 for bit[0].

0 = CPU cannot write the registers[a]

1 = CPU can access the registersa.

[2]
[1]
[0]

[a] The accessible registers are the SAC Register, the SCU Control Register, the SCU CPU Status Register, the filtering registers, and the SCU CPU Power Status Register.


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