In the Cortex-A9 MPCore implementation, the debug interface of each individual Cortex-A9 processor is exported to the MPCore boundary, so that each individual Cortex-A9 can be debugged independently.

Multi-processing debug capabilities, such as cross-triggering, can be configured externally to the Cortex-A9 MPCore. See the CoreSight v1.0 Architecture Specification and ARM Debug Interface v5 Architecture Specification.

Figure 6.1 shows the CortexA9 MP external debug interface signals.

A few signals on the Cortex-A9 MPCore debug interface are common to all Cortex-A9 processors in the cluster. This is the case for the APB debug interface. See Cortex-A9 MPCore APB Debug interface and memory map.

The CortexA9 MPCore external debug interface does not implement: