2.2.1. SCU Control Register

The SCU Control Register characteristics are:

  • enables speculative linefills to L2 with L2C-310

  • enables Force all Device to port0

  • enables IC standby mode

  • enables SCU standby mode

  • enables SCU RAM parity support

  • enables address filtering

  • enables the SCU.

Usage constraints
  • This register is writable in Secure state if the relevant bit in the SAC register is set.

  • This register is writable in Non-secure state if the relevant bits in the SAC and SNSAC registers are set.


Available in all Cortex-A9 multiprocessor configurations.


See the register summary in SCU registers.

Figure 2.1 shows the SCU Control Register bit assignments.

Figure 2.1. SCU Control Register bit assignments

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Table 2.2 shows the SCU Control Register bit assignments.

Table 2.2. SCU Control Register bit assignments

Bits NameFunction
[6] IC standby enable

When set, this stops the Interrupt Controller clock when no interrupts are pending, and no CPU is performing a read/write request.

This bit is set to 0 by default

[5]SCU standby enable

When set, SCU CLK is turned off when all processors are in WFI mode, there is no pending request on the ACP, if implemented, and there is no remaining activity in the SCU.

When SCU CLK is off, ARREADYS, AWREADYS and WREADYS on the ACP are forced LOW. The clock is turned on when any processor leaves WFI mode, or if there is a new request on the ACP.

This bit is set to 0 by default

[4]Force all Device to port0 enable

When set, all requests from the ACP or processors with AxCACHE = Noncacheable Bufferable are forced to be issued on the AXI Master port M0. See Address filtering capabilities.

This bit is set to 0 by default

[3]SCU Speculative linefills enable

When set, coherent linefill requests are sent speculatively to the L2C-310 in parallel with the tag look-up. If the tag look-up misses, the confirmed linefill is sent to the L2C-310 and gets RDATA earlier because the data request was already initiated by the speculative request. This feature works only if the L2C-310 is present in the design.

This bit is set to 0 by default

[2]SCU RAMs Parity enable

1 = Parity on.

0 = Parity off. This is the default setting.

This bit is always zero if support for parity is not implemented.

[1]Address filtering enable

1 = Addressing filtering on.

0 = Addressing filtering off.

The default value is the value of FILTEREN sampled when nSCURESET is deasserted.

This bit is always zero if the SCU is implemented in the single master port configuration. See Address filtering capabilities.

[0]SCU enable

1 = SCU enable.

0 = SCU disable. This is the default setting.

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