A.13.4. Miscellaneous debug interface signals

Table A.33 shows the miscellaneous debug interface signals. The value of N is one less than the number of processors in your design.

Table A.33. Miscellaneous debug signals

NameI/O

Source or

destination

Description

COMMRX[N:0]

OExternal debugger or CoreSight Interconnect

Comms Channels Receive.

Receive portion of Data Transfer Register full flag:

0 = empty

1 = full.

COMMTX[N:0]O

Comms Channels Transmit.

Transmit portion of Data Transfer Register full flag:

0 = empty

1 = full.

DBGNOPWRDWN[N:0]ODebugger has requested a Cortex-A9 processor is not powered down.

DBGSWENABLE[N:0]

I

When LOW only the external debug agent can modify debug registers.

0 = not enabled.

1 = enabled. Access by the software through the extended cp14 interface is permitted. External cp14 and external debug accesses are permitted.

DBGROMADDR[31:12]ICoreSight System configuration

Specifies bits [31:12] of the ROM table physical address.

If the address cannot be determined tie this signal off to zero.

DBGROMADDRVI

Valid signal for DBGROMADDR.

If the address cannot be determined tie this signal LOW.

DBGSELFADDR[31:15]I

Specifies bits [31:15] of the two’s complement signed offset from the ROM Table physical address to the physical address where the debug registers are memory-mapped.

If the offset cannot be determined tie this signal off to zero.

DBGSELFADDRVI

Valid signal for DBGSELFADDR.

If the offset cannot be determined tie this signal LOW.


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