2.2.3. SCU CPU Power Status Register

The SCU CPU Power Status Register characteristics are:

Purpose

Specifies the state of the Cortex-A9 processors with reference to power modes

Usage constraints

This register is writable in Secure state if the relevant bit in the SAC register is set.

This register is writable in Non-secure state if the relevant bits in the SAC and SNSAC registers are set.

Dormant mode and powered-off mode are controlled by an external power controller. SCU CPU Status Register bits indicate to the external power controller the power domains that can be powered down.

Before entering any other power mode than Normal, the Cortex-A9 processor must set its status field to signal to the power controller the mode it is about to enter. The Cortex-A9 processor then executes a WFI entry instruction. When in WFI state, the PWRCTLOn bus is enabled and signals to the power controller what it must do with power domains.

The SCU CPU Power Status Register bits can also be read by a Cortex-A9 processor exiting low-power mode to determine its state before executing its reset setup.

Cortex-A9 processors status fields take PWRCTLIn values at reset, except for nonpresent Cortex-A9 processors. For nonpresent Cortex-A9 processors writing to this field has no effect.

Configurations

Available in all Cortex-A9 MPCore configurations.

Attributes

See the register summary in Table 2.1.

Figure 2.3 shows the SCU CPU Power Status Register bit assignments.

Figure 2.3. SCU CPU Power Status Register bit assignments

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Table 2.4 shows the SCU CPU Power Status Register bit assignments.

Table 2.4. SCU CPU Power Status Register bit assignments

BitsNameFunction
[31:26]-Reserved, SBZ
[25:24]CPU3 status

Power status of the Cortex-A9 processor:

b00: Normal mode.

b01: Reserved.

b10: the Cortex-A9 processor is about to enter, or is in, dormant mode. No coherency request is sent to the Cortex-A9 processor.

b11: the Cortex-A9 processor is about to enter, or is in, powered-off mode, or is nonpresent. No coherency request is sent to the Cortex-A9 processor.

The default value is b00 when CPU3 processor is present, else b11

[23:18]-Reserved, SBZ
[17:16]CPU2 status

Power status of the Cortex-A9 processor.

The default value is b00 when CPU2 processor is present, else b11

[15:10]-Reserved, SBZ
[9:8]CPU1 status

Power status of the Cortex-A9 processor.

The default value is b00 when CPU1 processor is present, else b11

[7:2]-Reserved, SBZ
[1:0]CPU0 status

Power status of the Cortex-A9 processor.

The default value is b00 when CPU0 processor is present, else b11


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