Cortex-A9 MPCore Technical Reference Manual: A.7.1. AXI Master0 signals

The following sections describe the AXI Master0 interface signals:

Table A.10 shows the write address signals for AXI Master0.

Table A.10. Write address signals for AXI Master0

Name	I/O	Source or Destination	Description
AWADDRM0[31:0]	O	L2C-310 or other system AXI devices	Address.
AWBURSTM0[1:0]	O		Burst type Cortex-A9 processors can only issue INCR (BURST = 01) incrementing bursts. In the case of writes from the ACP, the burst type can also be FIXED (BURST = 00) or WRAP (BURST = 10) and these values can be forwarded onto the AXI Master0 port. Other values are Reserved.
AWCACHEM0[3:0]	O		Cache type giving additional information about cacheable characteristics set by the memory type and Outer cache policy.
AWIDM0[5:0]	O		Request ID See AWIDMx[5:0] encodings.
AWLENM0[3:0]	O	L2C-310 or other system AXI devices	The number of data transfers that can occur within each burst.
AWLOCKM0[1:0]	O		Lock type.
AWPROTM0[2:0]	O		Protection Type.
AWREADYM0	I		Address ready.
AWSIZEM0[1:0]	O		Burst size: b00 = 8-bit transfer b01 = 16-bit transfer b10 = 32-bit transfer b11 = 64-bit transfer.
AWUSERM0[8:0]	O		[8] early BRESP. Used with the L2C-310. [7] full line of zeros. Used with the L2C-310. [6] clean eviction. [5] level 1 eviction. [4:1] Memory type and inner cache policy. See AWUSERMx[8:0] encodings. [0] shared.
AWVALIDM0	O		Address valid.

Table A.11 shows the write data signals for AXI Master0.

Table A.11. Write data signals for AXI Master0

Name	I/O	Source or destination	Description
WDATAM0[63:0]	O	L2C-310 or other system AXI devices	Write data
WIDM0[5:0]	O		Write ID
WLASTM0	O		Write last indication
WREADYM0	I		Write ready
WSTRBM0[7:0]	O		Write byte lane strobe
WVALIDM0	O		Write valid

Table A.12 shows the write response signals for AXI Master0.

Table A.12. Write response signals for AXI Master0

Name	I/O	Source or destination	Description
BIDM0[5:0]	I	L2C-310 or other system AXI devices	Response ID
BREADYM0	O		Response ready
BRESPM0[1:0]	I		Write response
BVALIDM0	I		Response valid

Table A.13 shows the read address signals for AXI Master0.

Table A.13. Read address signals for AXI Master0

Name	I/O	Source or destination	Description
ARADDRM0[31:0]	O	L2C-310 or other system AXI devices	Address
ARBURSTM0[1:0]	O		Burst type: Cortex-A9 processors can only issue one of the two following AXI burst types: b01 = INCR incrementing burst b10 = WRAP Wrapping burst. In the case of writes from the ACP, the burst type can also be FIXED (BURST = 00) and this value can be forwarded onto the AXI Master0 port. Other values are Reserved.
ARCACHEM0[3:0]	O		Cache type giving additional information about cacheable characteristics.
ARIDM0[5:0]	O		Request ID See ARIDMx[5:0] encodings.
ARLENM0[3:0]	O		Burst length that gives the exact number of transfers.
ARLOCKM0[1:0]	O		Lock type.
ARPROTM0[2:0]	O		Protection Type
ARREADYM0	I		Address ready.
ARSIZEM0[1:0]	O	L2C-310 or other system AXI devices	Burst size: b00 = 8-bit transfer b01 = 16-bit transfer b10 = 32-bit transfer b11 = 64-bit transfer.
ARUSERM0[6:0]	O		Sideband information: [6] Speculative linefill, used with L2C-310 [5] prefetch hint, used with L2C-310 [4:1] inner attributes b0000 = Strongly-ordered b0001 = Device b0011 = Normal Memory Non-Cacheable b0110 = Write-Through b0111 = Write-Back no Write Allocate b1111 = Write-Back Write Allocate. [0] shared bit. See ARUSERMx[6:0] encodings.
ARVALIDM0	O		Address valid.

Table A.14 shows the interface signals on M0 for speculative read accesses between Cortex-A9MPCore and L2C-310.

Table A.14. L2C-310 signals on M0

Name	I/O	Source	Description
SRENDM0[3:0]	I	L2C-310	Speculative linefill confirmations from L2C-310.
SRIDM0[23:0]	I	L2C-310	Speculative confirmed IDs from L2C-310

Table A.15 shows the read data signals for AXI Master0.

Table A.15. Read data signals for AXI Master0

Name	I/O	Source or destination	Description
RVALIDM0	I	L2C-310 or other system AXI devices	Read valid
RDATAM0[63:0]	I		Read data
RRESPM0[1:0]	I		Read response
RLASTM0	I		Read Last indication
RIDM0[5:0]	I		Read ID
RREADYM0	O		Read ready

Table A.16 shows the AXI Master0 clock enable signals.

Table A.16. AXI Master0 clock enable signals

Name	I/O	Source	Description
INCLKENM0	I	Clock controller	Clock enable for the AXI bus that enables the AXI interface to operate at either: integer ratios of the system clock half integer ratios of the system clock. See Interfaces.
OUTCLKENM0	I	Clock enable for the AXI bus that enables the AXI interface to operate at either: integer ratios of the system clock half integer ratios of the system clock. See Interfaces.

Name

I/O

Source

Description

INCLKENM0

Clock

controller

Clock enable for the AXI bus that enables the AXI interface to operate at either:

OUTCLKENM0

Clock enable for the AXI bus that enables the AXI interface to operate at either:

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