2.2.4. SCU Invalidate All Registers in Secure State Register

The SCU Invalidate All Registers in Secure State characteristics are:

Purpose

Invalidates the SCU tag RAMs on a per Cortex-A9 processor and per way basis.

Usage constraints

This register:

  • Invalidates all lines in the selected ways.

  • Is a write-only register that always reads as zero.

Configurations

Available in all Cortex-A9 multiprocessor configurations.

Attributes

See the register summary in Table 2.1.

Figure 2.4 shows the SCU Invalidate All Register in Secure state bit assignments.

Figure 2.4. SCU Invalidate All Registers in Secure state bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 2.5 shows the SCU Invalidate All Register in Secure state bit assignments.

Table 2.5. SCU Invalidate All Registers in Secure state bit assignments

BitsNameFunction
[31:16]--
[15:12]CPU3 waysSpecifies the ways that must be invalidated for CPU3. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than four processors.
[11:8]CPU2 waysSpecifies the ways that must be invalidated for CPU2. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than three processors.
[7:4]CPU1 waysSpecifies the ways that must be invalidated for CPU1. Writing to these bits has no effect if the Cortex-A9 MPCore processor has fewer than two processors.
[3:0]CPU0 waysSpecifies the ways that must be invalidated for CPU0.

Copyright © 2008-2011 ARM. All rights reserved.ARM DDI 0407G
Non-ConfidentialID072711