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Table A.32 shows the CTI signals. The value of N is one less than the number of processors in your design.
Table A.32. Cross trigger interface signals
| Name | I/O | Source or destination | Description |
|---|---|---|---|
EDBGRQ[N:0] | I | External debugger or CoreSight interconnect | External debug request: 0 = no external debug request 1 = external debug request. The processor treats the EDBGRQ input as level sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK. |
DBGACK[N:0] | O | Debug acknowledge signal | |
DBGCPUDONE[N:0] | O | Debug acknowledge signal 0 = not enabled 1 = enabled. | |
DBGRESTART[N:0] | I | Causes the core to exit from Debug state. It must be held HIGH until DBGRESTARTED is deasserted. 0 = not enabled 1 = enabled. | |
DBGRESTARTED[N:0] | O | Used with DBGRESTART to move between Debug state and Normal state. 0 = not enabled 1 = enabled. |
| Copyright © 2008-2011 ARM. All rights reserved. | ARM DDI 0407G |
| Non-Confidential | ID072711 |
| PDF version | |
| Home > Signal Descriptions > External Debug interface > Cross trigger interface signals |