A.1. Clock and clock control signals

Table A.1 shows the clock and clock control signals.

Table A.1. Cortex-A9 MPCore clocks and clock control signals

NameI/OSourceDescription
CLKIClock controllerGlobal clock
MAXCLKLATENCY[2:0]IImplementation-specific static value

Control dynamic clock gating delays.These pins are sampled during reset of the processor.

PERIPHCLKIClock controllerClock for the timer and Interrupt Controller
PERIPHCLKENIClock controllerClock enable for the timer and Interrupt Controller

See Chapter 5 Clocks, Resets, and Power Management.

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