2.2.7. SCU Access Control Register (SAC)

The SAC characteristics are:

Purpose

Controls access to the following registers on a per Cortex-A9 processor basis:

A processor in the Cortex-A9 MPCore multiprocessor can set up the SCU and then write zero to the register. This prevents any Secure or Non-secure access from altering the configuration of the register again. This prevents any more changes to the SCU configuration after booting.

Usage constraints

This register is writable:

  • in Secure state if the relevant bit in the SAC register is set.

  • in Non-secure state if the relevant bits in the SAC and SNSAC are set.

Configurations

Available in all Cortex-A9 MPCore configurations.

Attributes

See the register summary in Table 2.1.

Figure 2.7 shows the SAC register bit assignments.

Figure 2.7. SAC register bit assignments

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Table 2.8 shows the SAC register bit assignments.

Table 2.8. SAC register bit assignments

Bits NameFunction
[31:4]SBZ-
[3]CPU3

0 = CPU3 cannot access the registers[a]

1 = CPU3 can access the registers. This is the default.

[2]CPU2

0 = CPU2 cannot access the registers.

1 = CPU2 can access the registers.This is the default.

[1]CPU1

0 = CPU1 cannot access the registers.

1 = CPU1 can access the registers. This is the default.

[0]CPU0

0 = CPU0 cannot access the registers.

1 = CPU0 can access the registers. This is the default.

[a] The accessible registers are the SAC Register, the SCU Control Register, the SCU CPU Status Register, the SCU Invalidate All Register in Secure State, the filtering registers, and the SCU CPU Power Status register.


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