Appendix B. Revisions

This appendix describes the technical changes between released issues of this books.

Table B.1. Issue A

First release-

Table B.2. Differences between issue A and issue B

Clarify the relationship between the GIC (PL390) and the Cortex-A9 Interrupt Controller

Chapter 3 Interrupt Controller.

Parity error option addedTable 1.1.
Clarify the role of the SCU with reference to data coherency and the non-support of instruction cache coherencyAbout the SCU.
Added information about exclusive accesses and address filteringAddress filtering on page 2-2.
SSAC description corrected

SCU Non-secure Access Control Register.

SSAC bit assignments correctedTable 2.9.
Change STI, Software Triggered Interrupt, to SGI, Software Generated Interrupt

Throughout Chapter 3 Interrupt Controller.

INTID descriptions extended and clarified

Throughout Chapter 3 Interrupt Controller.

Reset information added

Timer and watchdog registers on page 5-3.

AXI transaction IDs section extended

AXI transaction IDs on page 6-3.

AXI USER encodings section added

AXI USER encodings on page 6-5.

EVENTI information extended and EVENTO information addedWFE/SEV synchronization on page 6-9.

CLUSTERID[3:0] description corrected

Configuration signals.
DBGEN[3:0] description added

Table A.30.

Differences between issue B and issue C

Table B.3. Differences between issue B and issue C

Design changes listed Product revisions.
New entries in the Private Memory mapTable 2-2 on page 2-3.
Timers and watchdogs renamed Private timers and watchdogsTable 2-2 on page 2-3.
TLB size added as a configurable optionTable 1.1.
Timing diagrams addedFigure 1-4 on page 1-25, Figure 1-5 on page 1-25, Figure 1-6 on page 1-26, and Figure 1-7 on page 1-26.
CPUCLKOFF and DECLKOFF added to Power-on resetCortex-A9 MPCore reset on page 1-28. Configuration signals.
Correction to Tag RAM sizes valuesTable 2.3
Change in SCU Power Status Register layoutSCU CPU Power Status Register on page 2-7
Additional PPI. There are five PPIs per Cortex-A9 processor interfaceInterrupt types and sources on page 3-2.
PPI(4) added to the PPI Status RegisterPPI Status Register.
INT renamed IRQSSPI Status Registers. Interrupts.
Chapter 5 renamed. It was “Private timers and Watchdog Registers”.Chapter 4 Global timer, private timers, and watchdog registers.
L2 interface chapter included in Chapter 1 
nIRQOUT[N:0] and nFIQOUT[N:0] addedInterrupts.
MAXCLKLATENCY[2:0] addedConfiguration signals.
BISTCLAMP removedPower management signals.
AXI descriptions corrected and extendedAXI interfaces.
AXI Master1 descriptions removed.
AWLOCKS[1:0] corrected to AWLOCKS[0].Table A.17.
ARIDS[5:0] corrected to ARIDS[2:0].Table A.20.
Performance monitoring signals extended and new signals added.Performance monitoring signals.
SCUEVABORT moved to Performance Monitoring from Parity error signals section.Performance monitoring signals.
SCANMODE removedScan test signal.
PRDATADBG corrected to PRDATADBG[31:0]Table A.31.
WPTT32nT16n changed to WPT32LINKnTable A.34.

Differences between issue C and issue D.

Table B.4. Differences between issue C and issue D

Global timer re-positioned. Other timers re-named private timers.Figure 1.1
Table 1-1 AXI master interface attributes movedTable 2.10
Table 1-2 ARID encodings movedTable 2.11
Table 1-3 AWIDMx encodings movedTable 2.12
Compliance content moved and extendedAbout Cortex-A9 MPCore coherency
Features list removed-
Configurable options includes Preload Engine options and ARM_BISTConfigurable options
Interfaces section extendedInterfaces
Private Memory Region chapter removed-
Private Memory Region content re-arranged. Table addedPrivate Memory Region
SLVERR changed to DECERRTable 1.2
Interfaces section extendedInterfaces
MPCore Considerations section addedMPCore considerations
Table 1-4 ARUSERMx[6:0]movedTable 2.12
Table 1-5 AWUSERMx[8:0] encodings movedTable 2.14
Table 1-6 Core mode and APROT values removed-
Figure 1-2 movedFigure 6.1
Figure 1-3 Three-to-one timing ratio movedFigure 5.1
Figure 1-4 movedFigure 2.9
Figure 1-5 movedFigure 2.10
Figure 1-6 movedFigure 2.11
Figure 1-7 movedFigure 2.12
Figure 1-8 movedFigure 2.12
Figure 1-9 moved and renamedFigure 5.2
Table 1-7 Configurable options movedTable 1.1
Table 1-8 PADDRDBG width replaced and extended Cortex-A9 MPCore APB Debug interface and memory map
Table 1-9 Cortex-A9 MPCore reset signals movedTable 5.1
Table 1-10 Cortex-A9 MPCore power modes movedTable 5.2
Table 2-1 Cortex-A9 MPCore memory region movedTable 1.3
ACP behavior description moved and extendedAccelerator Coherency Port
Design changes list extended Product revisions.
Snoop Control Unit chapter updated and extended to include detailed interface descriptionsChapter 2 Snoop Control Unit
SCU Register updatesTable 2.1
Interfaces SCU Control Register
Table 3-1 SCU registers summary moved and correctedTable 2.1
Table 3-2 moved and retitledTable 2.2
Figure 3-1 SCU Control Register format moved and retitledFigure 2.1
Table 3-3 moved and retitledTable 2-3
Figure 3-2 moved and retitledFigure 2.2
Table 3-4 moved and retitledTable 2.4
Figure 3-3 moved and retitledFigure 2.3
Table 3-5 moved and retitledTable 2.5
Figure 3-4 SCU Invalidate All Registers in Non-secure state format removed-
Table 3-5 removed-
Figure 3-5 SCU Invalidate All Registers in Secure state format movedFigure 2.4
Table 3-6 movedTable 2.5
Figure 3-6 movedFigure 2.5
Table 3-7 movedTable 2.6
Figure 3-7 movedFigure 2.6
Table 3-8 movedTable 2.7
Figure 3-8 movedFigure 2.7
Table 3-9Table 2.8
Figure 3-9 renamed and movedFigure 2.8
Table 3-10Table 2.9
Removal of content that repeats GIC Architecture contentChapter 3 Interrupt Controller
Re-organization of remaining Interrupt Controller content 
4.2 TrustZone support renamed and specification content removedSecurity extensions support
4.3 About the Interrupt Distributor removed-
4.4 Interrupt Distributor interrupt sources removed-
4.5 Cortex-A9 processor interfaces removed-
Interrupt security registers removed-
Enable set registers removed-
Enable clear registers removed-
Pending set registers removed-
Pending clear registers removed-
Active status registers removed-
Interrupt Priority Registers removed-
Interrupt Processor Targets Registers removed-
Interrupt Configuration Registers removed-
Software Generated Interrupt Register removed-
CPU Interface Control Register removed-
Interrupt Priority Mask Register removed-
Binary Point Register removed-
Interrupt Acknowledge Register removed-
End Of Interrupt Register removed-
Running Priority Register removed-
Highest Pending Interrupt Register removed-
Chapter 5 Timer and Watchdog Registers updated and correctedChapter 4 Global timer, private timers, and watchdog registers
5.1 About the timer and watchdog blocks renamedAbout the private timer and watchdog blocks
Table 5-1 movedTable 4.1
5.2 Timer and watchdog registers moved and renamedPrivate timer and watchdog registers
Note about private timer behavior added below Table 4-1Table 4.1
Corrections to Timer Control Register sectionPrivate Timer Control Register
Corrections to Timer Interrupt Status RegisterPrivate Timer Interrupt Status Register
Clarification of behavior in relation to Interrupt ID 29Private Timer Interrupt Status Register
Comparator Value Registers, 0x10 and 0x14 moved and correctedComparator Value Registers, 0x10 and 0x14
Auto-increment Register, 0x18 moved and correctedAuto-increment Register, 0x18
5.3 About the Global Timer moved and correctedAbout the Global Timer
Global Timer Control Register section addedGlobal Timer Control Register
Global Timer Interrupt Status Register addedGlobal Timer Interrupt Status Register
Resets descriptions revised and extendedResets
Signals lists updatedSource or destination column added to all signal lists
nNEONRESET[N:0] replaces nDERESET[N:0]Table A-2
CP15 c15 Configuration Base Address Register replaces System Control Config base Register
Power control signal descriptions corrected and clarified.
SCUIDLE signal added
Duplicated AXI user encodings removedTable A.10
ARUSERM0[6:0] correctedTable A.13

Speculative read interface signals section added

Speculative read interface signals for M0
[4:0] in AWUSERS[4:0] corrected to [4:1]Table A.17
NEON SIMD unit replaces MPETable A.23

PMUEVENT size becomes 57 bits

DEFLAGS and SCUEVABORT have a separate tableException flags signals
PARITYSCU[3:0] becomes PARITYFAILSCU[N:0]Table A.25
MBISTBE[31:0] becomes MBISTBE[32:0]Table A.27
Description of DBGSWENABLE[N:0] amendedTable A.33
DBGSELFADDR bits corrected to [31:15]
WPTCOMMITn bits corrected to [1:0]Table A.34
WPT32LINKn corrected toWPTT32LINKn
Statement about WPTTARGETTBIT removed

Table B.5. Differences between D and F

Document title corrected to AMBA® Level 2 Cache Controller (L2C-310) Technical Reference ManualAdditional reading
PL310 corrected to L2C-310 throughout-
Symmetric configurations corrected to uniform configurationsAbout the Cortex-A9 MPCore processor
Tag RAMs renamed to Cache line directoryFigure 1.1
Coherency description reworded for clarityAbout Cortex-A9 MPCore coherency
SCU control register correctionsSCU Control Register
Values correctedTable 2.10
Note about theoretical maximums addedAXI issuing capabilities
Corrections to INCR valuesCortex-A9 MPCore AXI transactions
Note about transactions added
Data linefill buffer correctedTable 2.11
Clarification about ratios addedAXI master interface clocking
Removed incorrect cross referencesChapter 3 Interrupt Controller
Register names aligned with GIC Architecture namesChapter 3 Interrupt Controller
Access description correctedAbout the Interrupt Controller
Corrected information about interrupt sourcesInterrupt Distributor interrupt sources
Paragraph about single processor designs movedInterrupt Processor Targets Registers
Second line correctedTable 3.1
Interrupt Configuration Registers section addedInterrupt Configuration Registers
Values column added to Table 3-5Table 3.5
Inputs clarified.PPI Status Register
Address offset sentence below Figure 3-6 removedFigure 3.6
PrimeCell Identification Registers section removed-
Description of prescaler added to features listAbout the private timer and watchdog blocks
PERIPHCLK added as reference clockPrivate Timer Control Register
Global timer behavior feature addedAbout the Global Timer
Comparator register offsets addedComparator Value Registers, 0x10 and 0x14
No asynchronous interfaces information addedClocks
Reset descriptions expanded and clarifiedResets
IEM section removedPower management
Rewritten and extendedStandby modes
WFI replaced by StandbyPower management
Lead processor replaced by primary processorMultiprocessor bring-up
Missing [N:0] added to signal namesTable A.3
Signal descriptions correctedWFE and WFI Standby signals
Table A.8
STATIC replaced by FIXEDTable A.10
AWBURSTM0[1:0] description expanded
AWCACHEM0[3:0] description expanded
AWLENM0[3:0] corrected, repeated AXI information removed
AWLOCKM0[1:0] corrected, repeated AXI information removed
AWUSERM0[8:0] description corrected
ARBURSTM0[1:0] corrected and expandedTable A.13
ARLENM0[3:0] corrected, repeated AXI information removedTable A.13
ARLOCKM0[1:0] corrected, repeated AXI information removedTable A.13
AWBURSTS[1:0] corrected, repeated AXI information removedTable A.17
AWLENS[3:0] description expanded and corrected Table A.17
STATIC replaced by FIXEDTable A.20
ARBURSTS[1:0] corrected, repeated AXI information removed
ARLENS[3:0] corrected, repeated AXI information removed
ARLOCKS[1:0] corrected, repeated AXI information removed
SCUEVABORT description correctedTable A.24

Table B.6. Differences between issue F and issue G

Correct section title for Read address signalsRead address signalsAll releases
ACP interface clocking moved to Accelerator Coherency Port SectionACP interface clocking-All releases
Correct description of Read address channelRead address channel signalsAll releases
Correct description of Clock enable slave signalClock enable slave signalAll releases
Power management standby modes section updatedStandby modesAll releases
Update interrupt controller behaviorCortex-A9 MPCore 1-N interrupt model handlingAll releases
Update AXI master interface timing diagramsAXI master interface clockingAll releases

Updated SCU register summary table to include security state

Table 2.1All releases
Updated information about Tag RAM sizesTable 2.3All releases
Updated description of SCU Invalidate All Registers in Secure StateSCU Invalidate All Registers in Secure State RegisterAll releases
Updated description of SAC and SNSACTable 2.8Table 2.9All releases
Updated description of ACP functional limitationsACP functional limitationsAll releases
Updated interrupt controller description

About the Interrupt Controller

Interrupt Distributor interrupt sources

Interrupt Distributor arbitration

All releases
Updated ICDDCR usage constraintsDistributor Control RegisterAll releases
Updated SCU CPU Power Status Register reset valueTable 2.2All releases

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