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Table 1.1 shows the Cortex-A9 MPCore processor configurable options.
Table 1.1. Configurable options for the Cortex-A9 MPCore processor
| Feature | Options |
|---|---|
| Cortex-A9 processors | One to four |
| Instruction cache size per Cortex-A9 processor | 16KB, 32KB, or 64KB |
| Data cache size per Cortex-A9 processor | 16KB, 32KB, or 64KB |
| TLB size per Cortex-A9 processor | 64 entries or 128 entries |
Media Processing Engine with NEON technology per Cortex-A9 processor[a] | Included or not |
FPU per Cortex-A9 processor[b] | Included or not |
| Preload Engine per Cortex-A9 processor | Included or not |
| Number of entries in the Preload Engine FIFO per Cortex-A9 processor | 16, 8, or 4 |
| Jazelle DBX extension per Cortex-A9 processor | Full or trivial |
| Program Trace Macrocell (PTM) interface per Cortex-A9 processor | Included or not |
| Power off and dormant mode wrappers | Included or not |
| Support for parity error detection[c] | Included or not |
| ARM_BIST | Included or not |
| Master ports | One or two |
| Accelerator Coherency Port | One, included or not |
| Shared Peripheral Interrupts (SPIs) | 0-224, in steps of 32 |
[a] Includes support for floating-point operations. If this option is implemented then the FPU option cannot also be implemented. [b] If this option is implemented then the Media Processing Engine with NEON technology option cannot also be implemented. [c] The Cortex-A9 TRM describes the parity error scheme. See Parity error signals for a description of the signals. | |
| Copyright © 2008-2011 ARM. All rights reserved. | ARM DDI 0407G |
| Non-Confidential | ID072711 |
| PDF version | |
| Home > Introduction > Configurable options |