1.5. Private Memory Region

All registers accessible by all Cortex-A9 processors within the Cortex-A9 MPCore are grouped into two contiguous 4KB pages accessed through a dedicated internal bus. The base address of these pages is defined by the pins PERIPHBASE[31:13]. See Configuration signals for more information on PERIPHBASE[31:13].

Cortex-A9 MPCore global control and peripherals must be accessed through memory-mapped transfers to the Cortex-A9 MPCore private memory region.

Memory regions used for these registers must be marked as Device or Strongly-ordered in the translation tables.

Access to the private memory region is little-endian only.

Access these registers with single load/store instructions. Load or store multiple accesses cause an abort to the requesting Cortex-A9 processor and the Fault Status Register shows this as a SLVERR

Table 1.2 shows the permitted access sizes for the private memory regions.

Table 1.2. Permitted access sizes for private memory regions

Private memory regionPermitted access sizes
ByteHalfword[a]Word[b]Doubleword[a]
Global timer, private timers, and watchdogs NoNoYesNo
SCU registersYesNoYesNo
Cortex-A9 processor interrupt interfaces
Interrupt distributor

[a] Halfword or doubleword accesses cause an abort to the requesting Cortex-A9 processor and the Fault Status Register shows this as a SLVERR

[b] A word access with strobes not all set causes an abort to the requesting Cortex-A9 processor and the Fault Status Register shows this as a SLVERR.


The Accelerator Coherency Port (ACP) cannot access any of the registers in this memory region.

Table 1.3 shows register addresses for the Cortex-A9 MPCore processor relative to this base address.

Table 1.3. Cortex-A9 MPCore private memory region

Offset from

PERIPHBASE[31:13]

PeripheralDescription
0x0000 - 0x00FCSCU registersChapter 2 Snoop Control Unit
0x0100 - 0x01FFInterrupt controller interfaces Chapter 3 Interrupt Controller
0x0200 - 0x02FFGlobal timerAbout the Global Timer
0x0300 - 0x03FF--
0x0400 - 0x04FF--
0x0500 - 0x05FF--
0x0600 - 0x06FFPrivate timers and watchdogs Private timer and watchdog registers
0x0700 - 0x07FF

Reserved

Any access to this region causes a SLVERR abort exception

0x0800 - 0x08FF
0x0900 - 0x09FF
0x0A00 - 0x0AFF
0x0B00 - 0x0FFF
0x1000 - 0x1FFFInterrupt DistributorInterrupt Distributor interrupt sources

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