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The reset signals present in the Cortex-A9 MPCore processor design enable you to reset different parts of the design independently. Table 5.1shows the different reset combinations that can be expected in a Cortex-A9 MPCore system. [n] refers to the Cortex-A9 processor that initiates a reset.
Table 5.1. Reset combinations in a Cortex-A9 MPCore system
nSCURESET and | nCPURESET[3:0] | nNEONRESET[3:0] | nDBGRESET[3:0] | nWDRESET[3:0] | |
---|---|---|---|---|---|
nPERIPHRESET | |||||
Cortex-A9 MPCore Power on reset | 0 | All 0 | All 0 | All 0 | All 0 |
Cortex-A9 MPCore Software reset | 0 | All 0 | All 0 | All 1 | All 0 |
Per processor Power on reset | 1 | [n]=0 | [n]=0 | [n]=0 | [n]=0 or all 1 |
Per processor Software reset | 1 | [n]=0 | [n]=0 | All 1 | [n]=0 or all 1 |
SIMD MPE power on | 1 | All 1 | [n]=0 | All 1 | All 1 |
Cortex-A9 MPCore Debug | 1 | All 1 | All 1 | All 0 | All 1 |
Per processor Debug | 1 | All 1 | All 1 | [n]=0 | All 1 |
Per processor Watchdog flag | 1 | All 1 | All 1 | All 1 | [n]=0 |
The following sections describe the reset combinations: