3.1.2. Interrupt Distributor interrupt sources

Interrupt sources for the Interrupt Distributor are of the following types:

Software Generated Interrupts (SGI)

Each Cortex-A9 processor has private interrupts, ID0-ID15, that can only be triggered by software. These interrupts are aliased so that there is no requirement for a requesting Cortex-A9 processor to determine its own CPU ID when it deals with SGIs. The priority of an SGI depends on the value set by the receiving Cortex-A9 processor in the banked SGI priority registers, not the priority set by the sending Cortex-A9 processor.

Global timer, PPI(0)

The global timer uses ID27.

A legacy nFIQ pin, PPI(1)

In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor.

When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28.

Private timer, PPI(2)

Each Cortex-A9 processor has its own private timers that can generate interrupts, using ID29.

Watchdog timers, PPI(3)

Each Cortex-A9 processor has its own watchdog timers that can generate interrupts, using ID30.

A legacy nIRQ pin, PPI(4)

In legacy IRQ mode the legacy nIRQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor.

When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nIRQ pin is treated like other interrupt lines and uses ID31.

Shared Peripheral Interrupts (SPI)

SPIs are triggered by events generated on associated interrupt input lines. The Interrupt Controller can support up to 224 interrupt input lines. The interrupt input lines can be configured to be edge sensitive (positive edge) or level sensitive (high level). SPIs start at ID32.

A unique ID identifies interrupt sources, except the SGIs that are aliased and identified by CPU source.

All interrupt sources have their own configurable priority.

All interrupt sources, except the SGIs and PPIs, also have their own configurable CPU target list, that is, a list of Cortex-A9 processors where the interrupt is sent when triggered by the Interrupt Distributor.

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