3.1.4. Cortex-A9 MPCore 1-N interrupt model handling

In systems with two or more processors, if an interrupt is received by more than one processor, the Cortex-A9 MPCore ensures that only one of the processors reads the corresponding interrupt ID. This removes the requirement for a lock on the Interrupt Service Routine.

When accessing the ICCIAR register, other processors then read the spurious ID, or another pending ID.

Copyright © 2008-2011 ARM. All rights reserved.ARM DDI 0407G