3.3.6. Interrupt Processor Targets Registers

This section describes the implementation defined features of the ICDIPTRn.

For systems that support only one Cortex-A9 processor, all these registers read as zero, and writes are ignored. The single Cortex-A9 processor is always set as the target of any interruption.

For systems that support two or more Cortex-A9 processors, if the Processor Target field is set to 0 for a specific SPI, then this interrupt cannot be set pending through the hardware pins, nor by a write to the Set-Pending register.

Copyright © 2008-2011 ARM. All rights reserved.ARM DDI 0407G
Non-ConfidentialID072711