3.3.7. Interrupt Configuration Registers

This section describes the implementation defined features of the ICDICFR. Each bit-pair describes the interrupt configuration for an interrupt. The options for each pair depend on the interrupt type as follows:


The bits are read-only and a bit-pair always reads as b10.


The bits are read-only

PPI[1] and [4]:b01

interrupt is active LOW level sensitive.

PPI[0], [2],and[3]:b11

interrupt is rising-edge sensitive.


The LSB bit of a bit-pair is read-only and is always b1. You can program the MSB bit of the bit-pair to alter the triggering sensitivity as follows:


interrupt is active HIGH level sensitive


interrupt is rising-edge sensitive.

There are 31 LSPIs, interrupts 32-62. You can configure and then lock these interrupts against more change using CFGSDISABLE. The LSPIs are present only if the SPIs are present.

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