3.3.2. Interrupt Controller Type Register

The ICDICTR characteristics are:


Provides information about the configuration of the Interrupt Controller.

Usage constraints

There are no usage constraints.


Available in all Cortex-A9 MPCore configurations.


See the register summary in Table 3.1.

Figure 3.3 shows the ICDICTR bit assignments.

Figure 3.3. ICDICTR bit assignments

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Table 3.4 shows the ICDICTR bit assignments.

Table 3.4. ICDICTR bit assignments


Returns the number of Lockable Shared Peripheral Interrupts (LSPIs) that the controller contains. The encoding is:

b11111 = 31 LSPIs, that are the interrupts of IDs 32-62.

When CFGSDISABLE is HIGH, the interrupt controller prevents writes to any register location that controls the operating state of an LSPI.


Returns the number of security domains that the controller contains:

1 = the controller contains two security domains.

This bit always returns the value one.

[7:5]CPU number

The encoding is:

b000 the Cortex-A9 MPCore configuration contains one Cortex-A9 processor.

b001 the Cortex-A9 MPCore configuration contains two Cortex-A9 processors.

b010 the Cortex-A9 MPCore configuration contains three Cortex-A9 processors.

b011 the Cortex-A9 MPCore configuration contains four Cortex-A9 processors.

b1xx: Unused values.

[4:0]IT lines number

The encoding is:

b00000 = the distributor provides 32 interrupts[a], no external interrupt lines.

b00001 = the distributor provides 64 interrupts, 32 external interrupt lines.

b00010 = the distributor provides 96 interrupts, 64 external interrupt lines.

b00011 = the distributor provide 128 interrupts, 96 external interrupt lines.

b00100 = the distributor provides 160 interrupts, 128 external interrupt lines.

b00101 = the distributor provides 192 interrupts, 160 external interrupt lines.

b00110 = the distributor provides 224 interrupts, 192 external interrupt lines.

b00111 = the distributor provides 256 interrupts, 224 external interrupt lines.

All other values not used.

[a] The distributor always uses interrupts of IDs 0 to 31 to control any SGIs and PPIs that the Interrupt Controller might contain.

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