2.3.4. AXI USER attributes encodings

This section describes the implementation-specific AXI USER bit encodings on the master ports in the following sections:

ARUSERMx[6:0] encodings

This section describes the ARUSERMx[6:0] encodings for read transactions. As Table 2.13 shows, the value and the meaning of the ARUSERMx encodings depend on the source of the transaction. There are transactions originating from Cortex-A9 processors and transactions originating from the ACP:

  • ARIDMx[2] = 0 from one of the Cortex-A9 processors.

  • ARIDMx[2] = 1 from the ACP.

Table 2.13. ARUSERMx[6:0] encodings

 Transaction types
 

Cortex-A9 transactions

ARIDMx[2] = 0

ACP transactions

ARIDMx[2] = 1

ARUSERMx[6]

Speculative linefill to L2C-310

ACP USER bits

ARUSERMx[6:5] = 2'b00

ARUSERMx[5]

Prefetch hint

ARUSERMx[4:1]

Inner attributes

b0000 Strongly Ordered

b0001 Device

b0011 Normal Memory NonCacheable

b0110 WriteThrough

b0111 Write Back no Write Allocate

b1111 Write Back Write Allocate

ARUSERMx[4:1] = ARUSERSx[4:1]
ARUSERMx[0]

Shared bit

1 Coherent request

0 Non-coherent request


AWUSERMx[8:0] encodings

This section describes the AWUSERMx[8:0] encodings for write transactions. As Table 2.14 shows, the value and the meaning of the AWUSERMx encodings depend on the source of the transaction:

  • AWIDMx[2] = 0 from one of the Cortex-A9 processors.

  • AWIDMx[2] = 1 from the ACP.

Table 2.14. AWUSERMx[8:0] encodings

 Transaction types

Cortex-A9 transactions

AWIDMx[2] = 0

ACP transactions

AWIDMx[2] = 1

AWUSERMx[8]

Early BRESP enable

ACP USER bits

AWUSERMx[8:5] = 4'b0000

AWUSERMx[7]

Full line of write zeros indication

AWUSERMx[6]

Clean eviction information

AWUSERMx[5]

L1 eviction information

AWUSERMx[4:1]

Inner attributes:

b0000 Strongly Ordered

b0001 Device

b0011 Normal Memory NonCacheable

b0110 WriteThrough

b0111 Write Back no Write Allocate

b1111 Write Back Write Allocate.

AWUSERMx[4:0] = AWUSERS[4:0][a]
AWUSERMx[0]

Shared bit:

b0 Non-coherent request

b1 Coherent request.

[a] Each master agent connected to the ACP can specify its own AXI USER signals. However, to maintain consistency, ARM recommends that the ACP AXI USER signal encodings match those of the Cortex-A9 processors.


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