Cortex-A9 MPCore Technical Reference Manual: A.9. Exception flags signals

A.9. Exception flags signals

Table A.24 shows the DEFLAGS and SCUEVABORT signals.

Table A.24. Exception flags signals

Name	I/O	Destination	Description
DEFLAGSn[6:0]	O	System integrity controller	Data Engine output flags. Only implemented if the Cortex-A9 processor includes a Data Engine. If the DE is NEON SIMD unit: Bit[6] gives the value of FPSCR[27] Bit[5] gives the value of FPSCR[7] Bits[4:0] give the value of FPSCR[4;0]. If the DE is FPU: Bit[6] is zero. Bit[5] gives the value of FPSCR[7] Bits[4:0] give the value of FPSCR[4;0].
SCUEVABORT	O	Indicates an external abort has occurred during a coherency writeback.

Name

I/O

Destination

Description

DEFLAGSn[6:0]

System integrity controller

Data Engine output flags. Only implemented if the Cortex-A9 processor includes a Data Engine.

If the DE is NEON SIMD unit:

Bit[6] gives the value of FPSCR[27]
Bit[5] gives the value of FPSCR[7]
Bits[4:0] give the value of FPSCR[4;0].

If the DE is FPU:

Bit[6] is zero.
Bit[5] gives the value of FPSCR[7]
Bits[4:0] give the value of FPSCR[4;0].

SCUEVABORT

Indicates an external abort has occurred during a coherency writeback.

For additional information on the FPSCR, see the Cortex-A9 Floating-Point Unit (FPU) Technical Reference Manual and the Cortex-A9 NEON Media Processing Engine Technical Reference Manual.

Copyright © 2008-2011 ARM. All rights reserved.	ARM DDI 0407G
Non-Confidential	ID072711
PDF version