5.2.1. Cortex-A9 MPCore power-on reset

This power-on or cold reset initializes the whole logic in the Cortex-A9 MPCore processor.

You must apply power-on or cold reset to the Cortex-A9 MPCore processor when power is first applied to the system.

In the case of power-on reset, the leading (falling) edge of the reset signals does not have to be synchronous to CLK but the rising edge must be. This is achieved by using the CPUCLKOFF and NEONCLKOFF signals.You must assert the reset signals for at least nine CLK cycles to ensure correct reset behavior.

ARM recommends the following reset sequence on power-on:

  1. Apply all resets: nCPURESET, nDBGRESET, nWDRESET, nSCURESET, nPERIPHRESET, and nNEONRESET if the SIMD MPE is present.

  2. Apply at least nine CLK cycles, plus at least one cycle in each other clock domain, or more if the documentation for other components requests it. There is no harm in applying more clock cycles than this, and maximum redundancy can be achieved by applying 15 cycles on every clock domain.

  3. Assert all CPUCLKOFF signals with a value of 1’b1 and, if there is an SIMD MPE present, all NEONCLKOFF.

  4. Wait for the equivalent of approximately 10 cycles, depending on your implementation. This compensates for clock and reset tree latencies.

  5. Release resets.

  6. Wait for the equivalent of another approximately 10 cycles, again to compensate for clock and reset tree latencies.

  7. Deassert all CPUCLKOFF and NEONCLKOFF. This ensures that all registers in the design see the same CLK edge on exit from the reset sequence.

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