4.4.3. Global Timer Interrupt Status Register

This is a banked register for all Cortex-A9 processors present.

The event flag is a sticky bit that is automatically set when the Counter Register reaches the Comparator Register value. If the timer interrupt is enabled, Interrupt ID 27 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1. Figure 4.7 shows the Global Timer Interrupt Status Register bit assignment.

Figure 4.7. Global Timer Interrupt Status Register bit assignment

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Copyright © 2008-2011 ARM. All rights reserved.ARM DDI 0407G